No description available.

No description available.

No description available.

Stuttgart, Univ., Diss., 2004. / Computerdatei im Fernzugriff.

Stuttgart, Universiẗat, Diss., 2004.

No description available.

During the spring of 2016 the Swedish government presented a national IT-strategy involving personal computers for each student from grade 1-9. Meanwhile current studies are indicating the importance of handwriting for learning and remembering new skills. However, according to several cognitive scientists, the results from meta studies regarding analogue and digital tools and their contribution to learning processes are contradictory. A survey and a cross sectional study was therefore conducted aiming to compare analogue versus digital note taking and teaching methods. A total of 85 7:th grade students filled out a survey concerning their preferences in note taking and teaching methods. Non-parametric sign-test statistically proved the students in the study preferred typing over writing by hand when taking notes in class (p =0.008). Reasons for their preference included a general positive attitude towards using computers and students acknowledging the benefits of spelling programs. Furthermore, the students in the survey preferred their teacher using whiteboard instead of Powerpoint when lecturing (p=0.012). The students claimed to comprehend the content given in lectures more efficiently when whiteboard was utilized. The cross sectional study was performed in the purpose of comparing two note taking methods: writing by hand and typing. Two 7:th grade classes (N=39) participated in the study and a total of six theme lessons in ecology were conducted. The students’ individual performances were evaluated with exit tickets involving questions of facts and concepts. The differences between the classes’ performances were only marginal according to Mann-Whitney non-parametric analysis. Based on the results of this study, further implementation of computers in classrooms should be conducted methodically with care.

The design of mixed-signal integrated circuits has evolved from simple analog and digital circuits operating on the same silicon substrate to the point that now we have complete system on a chip solutions for communication systems. The levels of integration needed to remain cost effective in today's integrated circuit (IC) market require careful use of all the available die space. The current trend of digital to analog converter (DAC) design has focused on maximizing speed and linearity for high performance telecommunications systems. The circuit design methods used to achieve very high sample rates require the use of large amounts of die space. This thesis presents a 10-bit DAC that has been optimized for area, while still maintaining accurate operation at low frequencies. To achieve 10-bit performance, an ultra high gain op-amp is introduced for various servoing applications in the DAC. The architecture chosen for the DAC will show an optimization of required die size and performance when compared to other architectures. The DAC was fabricated in a standard digital 0.18 μm CMOS process. The DAC occupies 0.0104 mm² (110 μm x 94 μm), and only consumes 2.8 mW of power. In addition to the 10-bit DAC, a design is presented for a 13-bit DAC which occupies 0.020 mm², and requires only the addition of a minimum number of devices to the 10-bit DAC. / Graduation date: 2002

Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order ����� loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio of 10. / Graduation date: 2002

A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m CMOS technology. The system is fully differential and requires two non-overlapping clock phases to operate. The implementation of the calibration technique in the pipelined ADC is investigated. Simulation results show that 109dB of SNDR, 112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall accuracy of the ADC is 18 bits. / Graduation date: 2003