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在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。 / 基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。 / 本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。 / 在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。 / 本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。 / The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design. / Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on. / First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported. / Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB. / Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Bing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese. / Abstracts of thesis entitled: --- p.I / 摘 要 --- p.V / Contents --- p.VII / List of Figures --- p.XI / List of Tables --- p.XVI / Acknowledgement --- p.XVII / Chapter CHAPTER 1. --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Original contributions and outline of the thesis --- p.2 / References --- p.1 / Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3 / Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6 / Chapter 2.2 --- Mismatches in QBDSM --- p.8 / Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13 / Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13 / Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19 / Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20 / Chapter 2.3.4 --- Summary and Simulation Results --- p.27 / Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34 / Chapter 2.5 --- Measurement Results Analysis --- p.40 / Chapter 2.6 --- Conclusions --- p.47 / Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48 / Chapter A. --- I/Q Mismatch in Mixer --- p.48 / Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49 / Chapter C. --- I/Q Mismatch in QBDSM --- p.50 / Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51 / Chapter APPENDIX II: --- IRR Measurement Method --- p.52 / References --- p.56 / Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59 / Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61 / Chapter 3.1.1 --- Integrator Gain Error --- p.64 / Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65 / Chapter 3.1.3 --- Modulator Architecture --- p.66 / Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68 / Chapter 3.1.5 --- Noise Analysis --- p.69 / Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71 / Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73 / Chapter 3.2.2 --- Simulation Results --- p.75 / Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76 / Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77 / Chapter 3.3.2 --- Behavorial Simulation Results --- p.79 / Chapter 3.4 --- Jitter Analysis --- p.80 / Chapter 3.4.1 --- Jitter on Rising Edges --- p.81 / Chapter 3.4.2 --- Duty cycle jitter --- p.84 / Chapter 3.5 --- Prototyping Modulator Design --- p.85 / Chapter 3.6 --- Measurement Results --- p.89 / Chapter 3.7 --- Summary --- p.95 / References --- p.97 / Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105 / Chapter 4.1 --- Introduction --- p.105 / Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107 / Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107 / Chapter 4.2.2 --- Differential Sensing Mode --- p.111 / Chapter 4.3 --- Circuit Implementation --- p.114 / Chapter 4.4 --- Measurement Results --- p.117 / Chapter 4.5 --- Conclusion --- p.125 / Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126 / References --- p.127 / Chapter CHAPTER 5. --- Conclusions and future works --- p.129 / Chapter 5.1 --- Conclusions --- p.129 / Chapter 5.2 --- Future works --- p.130 / Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.