The widespread use of embedded mixed-signal cores in system-on-chip (SoC) or System-on-Package (SoP) design has been increasingly important in cost-effective manufacturing test for mixed-signal devices. A typical SoP encapsulates many of its internal functions, and its production test is performed by application of test signals to the SoP under control of external Automatic Test Equipment (ATE). However it is a problem that the external ATE does not have direct access to all the internal embedded functions of the SoP. Thus a classical test approach to SoP suffers from limited controllability and observability of its subsystems. Built-in Self-Test (BIST) and Built-off Self-test (BOST) schemes have been suggested and developed to overcome the limitations of conventional test, such as limited test Input/Output (I/O) accessibility as well as high test cost. However most BIST/BOST approaches have limited test accuracy. The focus of the dissertation is to develop a cost-effective performance-based test methodology based on BIST/BOST, while maintaining the same accuracy as conventional test. This dissertation proposes one BIST approach and two BOST schemes. Our BIST methodology presents a methodology for efficient prediction of circuit specifications with optimized signatures. The proposed Optimized Signature-Based Alternate Test (OSBAT) methodology accurately predicts the specifications of a Device Under Test (DUT) using a strong correlation mapping function. The approach overcomes the limitation that analytical expressions cannot precisely describe the nonlinear relationships between signatures and specifications. Our first BOST approach presents a practical methodology for effective prediction of individual dynamic performance parameters of differential devices with a cascaded Radio-Frequency (RF) transformer in loopback mode. The RF transformer produces differently weighted loopback responses, which are used to characterize the DUT dynamic performance. The approach overcomes the imbalance problem of Design for Test (DfT) circuitry on differential signaling, thereby accurately measuring the dynamic performance of differential mixed-signal circuits. The second BOST scheme is an efficient methodology for accurate prediction of aperture jitter using cost-effective loopback methodology. Aperture jitter is precisely separated from input and clock jitter as well as additive noise present in the DUT, by using an efficient loopback scheme. Hardware measurements were performed for all our approaches, and good results were obtained. This fact verifies that all approaches can be practically used for production test in industry.

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.