<p>This thesis is a part of an effort to make a scalable behavioral model of the Central Processing Unit and instruction set compatible with the DSP56000 Processor. The goal of this design is to reduce the critical path, silicon area, as well as power consumption of the instruction decoder.</p><p>The instruction decoder consists of three different types of operations instruction fetching, decoding and execution. By using these three steps an efficient model has to be designed to get the shortest critical path, less silicon area, and low power consumption.</p>

This thesis is a part of an effort to make a scalable behavioral model of the Central Processing Unit and instruction set compatible with the DSP56000 Processor. The goal of this design is to reduce the critical path, silicon area, as well as power consumption of the instruction decoder. The instruction decoder consists of three different types of operations instruction fetching, decoding and execution. By using these three steps an efficient model has to be designed to get the shortest critical path, less silicon area, and low power consumption.