In the process of continuous scaling improvement under a single system-on-chip which contains millions of logic gates, testability of the design becomes more and more important and thus multiple scan tree test architecture can effectively reduce test time and test data simultaneously. In the current two-dimensional structure of the system-level chip, the interconnect has become one of the main factors in delay and power consumption, and thus optimizing interconnect becomes a very important topic. Especially, three-dimensional ICs, stacked multiple chips vertically by through-silicon-via technique, can be effective in reducing the length of the interconnects, power consumption and offering features of heterogeneous IC integration. In this research study, we consider three-dimensional chips in both respects of wire length and the scan output limits, and propose the test synthesis algorithm of multiple scan trees to reduce test cost for three dimensional integrated circuits.