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IMPLEMENTING A TACTICAL TELEMETRY STYSTEM FOR MULTIPLE LAUNCH ROCKET SYSTEM (MLRS) STOCKPILE RELIABILITY TESTINGCox, Corry 10 1900 (has links)
International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes
Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase
the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing
SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical
Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing.
This paper will address a technical approach of how a small Tactical Telemetry System could be
built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor
fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit
in the nose area without altering the overall tactical rocket appearance or operation.
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Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-MemoryBreyer, Evelyn T., Mulaosmanovic, Halid, Trommer, Jens, Melde, Thomas, Dünkel, Stefan, Trentzsch, Martin, Beyer, Sven, Mikolajick, Thomas, Slesazeck, Stefan 23 June 2022 (has links)
Ferroelectric field-effect transistors (FeFET) based on hafnium oxide offer great opportunities for Logic-in-Memory applications, due to their natural ability to combine logic (transistor) and memory (ferroelectric material), their low-power operation, and CMOS compatible integration. Besides aggressive scaling, dense integration of FeFETs is necessary to make electronic circuits more area-efficient. This paper investigates the impact of ultra-dense co-integration of a FeFET and an n-type selector FET, sharing the same active area, arranged in a 2TNOR memory array. The examined FeFETs exhibit a very similar switching behavior as FeFETs arranged in a standard AND-type array, indicating that the ultra-dense co-integration does not degrade the FeFET performance, and thus, paves the path to a very fine-grained, ultra-dense Logic-in-Memory implementation. Based on this densely integrated 2TNOR array we propose a very compact design of a 4-to-1 multiplexer with a build-in look-up table, thus directly merging logic and memory.
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