Note:

With delay proportional to the logarithm of the multiplier word length, column compression multipliers are the fastest multipliers. Unfortunately, since the design community has assumed that fast multiplication can only be realized through custom design and layout, column compression multipliers are often dismissed as too timeconsuming and complex because of their irregular structure. This research demonstrates that an automated multiplier generation and layout process makes the column compression multiplier a viable option for application specific CMOS products. Techniques for optimal multiplier designs are identified through analysis of area, delay, and power characteristics of Wallace, Dadda, and Reduced Area multipliers. / text

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

by Ki-sing Ng. / Thesis (M.Phil.)--Chinese University of Hong Kong. / Bibliography: leaves 30.

Modular Multiplication is a time-consuming arithmetic operation because it involves multiplication as well as division. Modular exponentiation can be performed as a sequence of modular multiplications. Speeding the modular multiplication increases the speed of modular exponentiation. Modular exponentiation and modular multiplication are heavily used in current cryptographic systems. Well-known cryptographic algorithms, such as RSA and Diffie-Hellman key exchange, require modular exponentiation operations. Elliptic curve cryptography (ECC) needs modular multiplication. Information security is increasingly becoming very important. Encryption and Decryption are very likely to be in many systems that exchange information to secure, verify, or authenticate data. Many systems, like the Internet, cellular phones, hand-held devices, and E-commerce, involve private and important information exchange and they need cryptography to make it secure. There are three possible solutions to accomplish the cryptographic computation: software, hardware using application-specific integrated circuits (ASICs), and hardware using field-programmable gate arrays (FPGAs). The software solution is the cheapest and most flexible one. But, it is the slowest. The ASIC solution is the fastest. But, it is inflexible, very expensive, and needs long development time. The FPGA solution is flexible, reasonably fast, and needs shorter development time. Montgomery multiplication algorithm is a very smart and efficient algorithm for calculating the modular multiplication. It replaces the division by a shift and modulus-addition (if needed) operations, which are much faster than regular division. The algorithm is also very suitable for a hardware implementation. Many designs have been proposed for fixed precision operands. A word-based algorithm and the scalable Montgomery multiplier based on this algorithm have been proposed later. The scalable multiplier can be configured to meet the design area-time tradeoff. Also, it can work for any operand precision up to the memory capacity. In this thesis, we develop a prototyping environment that can be used to verify the functionality of the scalable Montgomery multiplier on the circuit level. All the software, hardware, and firmware components of this environment will be described. Also, we will discuss how this environment can be used to develop cryptographic applications or test procedures on top of it. We also present two FPGA designs of the processing unit of the scalable Montgomery multiplier. The FPGA design techniques that have been used to optimize these designs are described. The implementation results are analyzed and the designs are compared against each other. The FPGA implementation of the first design is also compared against its ASIC implementation. / Graduation date: 2003

Modular arithmetic operations (i.e., inversion, multiplication and exponentiation) are used in several cryptography applications, such as decipherment operation of RSA algorithm, Diffie-Hellman key exchange algorithm, elliptic curve cryptography, and the Digital Signature Standard including the Elliptic Curve Digital Signature Algorithm. The most important of these arithmetic operations is the modular multiplication operation since it is the core operation in many cryptographic functions. Given the increasing demands on secure communications, cryptographic algorithms will be embedded in almost every application involving exchange of information. Some of theses applications such as smart cards and hand-helds require hardware restricted in area and power resources. Cryptographic applications use a large number of bits in order to be considered secure. While some of these applications use 256-bit precision operands, others use precision values up to 2048 or 4096 such as in some exponentiation-based cryptographic applications. Based on this characteristics, a scalable multiplier that operates on any bit-size of the input values (variable precision) was recently proposed. It is replicated in order to generate long-precision results independently of the data path precision for which it was originally designed. The multiplier presented in this work is based on the Montgomery multiplication algorithm. This thesis work contributes by presenting a modified radix-4 Montgomery multiplication algorithm with new encoding technique for the multiples of the modulus. This work also describes the scalable hardware design and analyzes the synthesis results for a 0.5 ��m CMOS technology. The results are compared with two other proposed scalable Montgomery multiplier designs, namely, the radix-2 design, and the radix-8 design. The comparison is done in terms of area, total computational time and complexity. Since modular exponentiation can be generated by successive multiplication, we include in this thesis an analysis of the boundaries for inputs and outputs. Conditions are identified to allow the use of one multiplication output as the input of another one without adjustments (or reduction). High-radix multipliers exhibit higher complexity of the design. This thesis shows that radix-4 hardware architectures does not add significant complexity to radix-2 design and has a significant performance gain. / Graduation date: 2003

by Sin Yu Tsang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 40-42). / Chapter Chapter 1. --- Introduction --- p.1 / Chapter Chapter 2. --- Two-level structural equation model --- p.5 / Chapter Chapter 3. --- Estimation of the model under general constraints --- p.11 / Chapter Chapter 4. --- Estimation of the model under linear constraints --- p.22 / Chapter Chapter 5. --- Simulation results --- p.27 / Chapter 5.1 --- "Artificial examples for ""modified"" EM algorithm" --- p.27 / Chapter 5.2 --- "Artificial examples for ""restricted"" EM algorithm" --- p.34 / Chapter Chapter 6. --- Discussion and conclusion --- p.38 / References --- p.40 / Tables --- p.43

Thesis (Ph. D.)--University of Adelaide, Dept. of Pure Mathematics, 1984. / Includes bibliographical references.

Thesis (M.S.)--Oregon State University, 2004. / Printout. Includes bibliographical references (leaves 63-64). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2004. / Typescript (photocopy). Includes bibliographical references (leaves 53-54). Also available on the World Wide Web.