Residue codes have successfully been used for decades as a low overhead method of arithmetic error detection. This work explores the design space of residue checking for error detection in processors with modern word sizes and technology nodes. The area overheads of detecting arithmetic errors are considered for a variety of processor configurations, ranging from those best suited for embedded processors to those best for high-performance computers. The ultimate goal of this work is to enable the study of low overhead arithmetic error protection and correction in a wider variety of computer architectures than has previously been attempted in a systematic manner. / text