This bachelor thesis has been carried out at the company Didamus which is located in Mjärdevi, Linköping. The company is currently developing a dive-console which aims to take the scuba diving experience to a whole new level and also to make scuba diving more secure. An assembly of scuba divers that can communicate with each other during a dive session might be the difference between life and death. Many seas around the world have muddy water which means poor visibility. In each situation a computer providing a scuba diver with information about others connected to the network, hazardous accidents can possibly be avoided.  The network itself consist of 10 nodes that need a network protocol which provides stability and reliability for every participant. The nodes themselves have a distributed responsibility to make the network reliable. The type of network implemented was a regular Time Division Multiple Access (TDMA) network where different nodes were given permission to access the medium in different instances of time. A global reference of time is always needed in a TDMA network to make it function properly. In a typical TDMA network a GPS-service gives each and every node information about the global time.  Unfortunately, GPS-services do not work well in water so a Master-Slave method was used instead. The master provides the rest of the nodes in the network with a global time reference. After a successful reception of a global time reference, the slave will be granted access to the network. The communication between the nodes is based on ultrasonic waves propagating in the water. The velocity of ultrasonic waves in water is only 1500 meters per second, explained in Discovery of Sound in the Sea by University of Rhode Island, which is a relatively slow signal speed. With the slow velocity taken into account an efficient TDMA protocol was developed, to perform communication under water.

To have a well functioning and tailored network based on priorities and requirements is an important part of most modern companies. Network technicians that design these networks have very important tasks because many people rely on the solutions they chose to help them achieve many of their daily tasks.   This study focused on what you should think about when designing a network for a customer. Two simulated companies were created and modeled from real-world references. From their priorities and requirements a network proposal was created, suiting each company.   The companies were presented, along with an interview where the questions were used to gain the information necessary to reveal the clients needs. The answers were used as underlying motivation to what products and solutions were used to create the network proposals.   Different approaches on what is the most suitable for each company are discussed and hopefully these can be of use when designing networks in the future.

No description available.

The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication mechanisms between the increasing number of blocks, or cores, that can be integrated onto a single chip. The bus-based systems and point-to-point interconnection strategies in use today cannot be easily scaled to accommodate the large numbers of cores projected in the near future. Network-on-chip (NoC) interconnect infrastructures are one of the key technologies that will enable the emergence of many-core processors and systems-on-chip with increased computing power and energy efficiency. This dissertation is focused on testing, yield improvement and fault-tolerance of such NoC infrastructures. A fast, efficient test method is developed for NoCs, that exploits their inherent parallelism to reduce the test time by transporting test data on multiple paths and testing multiple NoC components concurrently. The improvement of test time varies, depending on the NoC architecture and test transport protocol, from 2X to 34X, compared to current NoC test methods. This test mechanism is used subsequently to perform detection of NoC link permanent faults, which are then repaired by an on-chip mechanism that replaces the faulty signal lines with fault-free ones, thereby increasing the yield, while maintaining the same wire delay characteristics. The solution described in this dissertation improves significantly the achievable yield of NoC inter-switch channels – from 4% improvement for an 8-bit wide channel, to a 71% improvement for a 128-bit wide channel. The direct benefit is an improved fault-tolerance and increased yield and long-term reliability of NoC based multicore systems.

Despite the importance of inter-cellular (between cell) communication networks in regulating homeostasis in multicellular organisms, very little is known about their topology, dynamics, or functional significance. Inter-cellular communication networks are particularly relevant in stem cell biology, as stem cell fate decisions (self-renewal, proliferation, lineage specification) are tightly regulated based on physiological demand. Using human blood stem cell cultures as an experimental paradigm, we present an integrated experimental and computational approach to interrogate a hierarchically organized tissue network. We have developed a novel mathematical model of blood stem cell development incorporating cell-level kinetic parameters as functions of secreted molecule-mediated inter-cellular networks. By relation to quantitative cellular assays, our model is capable of predictively simulating many disparate features of both normal and malignant hematopoiesis, relating internal parameters and microenvironmental variables to measurable cell fate outcomes. Through integrated in silico and experimental analyses we show blood stem and progenitor cell fate is regulated by cell-cell feedback, and can be controlled non-cell autonomously by dynamically perturbing inter-cellular signalling. Furthermore, we have compiled genome-scale molecular profiles (transcriptome and secretome), publicly available databases, and literature mining to reconstruct soluble factor-mediated inter-cellular signalling networks regulating cell fate decisions. We find that dynamic interactions between positive and negative regulators, in the context of tuneable cell culture parameters, tip the balance between stem cell supportive vs. non-supportive conditions. The cell-cytokine interactions can be summarized as an antagonistic positive-negative feedback circuit wherein stem cell self-renewal is regulated by a balance of megakaryocyte-derived stimulatory factors vs. monocyte-derived inhibitory factors. To understand how the experimentally identified positive and negative regulatory signals are integrated at the intra-cellular level, we define a literature-derived blood stem cell self-renewal network wherein these extracellular signals converge for coherent processing into cell fate decisions. In summary, this work demonstrates the utility of integrating experimental and computational methods to explore complex cellular systems, and represents the first attempt to comprehensively elucidate non-autonomous signals balancing stem cell homeostasis and regeneration.

The all terminal reliability of a graph G is the probability that at least a spanning tree is operational, given that vertices are always operational and edges independently operate with probability p in [0,1]. In this thesis, an investigation of all terminal reliability is undertaken. An open problem regarding the non-existence of optimal graphs is settled and analytic properties, such as roots, thresholds, inflection points, fixed points and the average value of the all terminal reliability polynomial on [0,1] are studied. A new reliability problem, the k -clique reliability for a graph G is introduced. The k-clique reliability is the probability that at least a clique of size k is operational, given that vertices operate independently with probability p in [0,1] . For k-clique reliability the existence of optimal networks, analytic properties, associated complexes and the roots are studied. Applications to problems regarding independence polynomials are developed as well.

No description available.

Distributed denial of service (DDoS) attacks are widely regarded as a major threat to the Internet. A flooding-based DDoS attack is a very common way to attack a victim machine by sending a large number of malicious traffic. In this thesis, we propose a distance-based distributed DDoS defense framework which defends against attacks by coordinating between the distance-based DDoS defense systems of the source ends and the victim end. The proposed defense system has three major components: detection, traceback, and response. In the detection component, two distance-based detection techniques are employed. First, a distance-based technique is used to detect attacks based on a distance statistical model. Second, a statistical traffic rate forecasting technique is applied to identify attack traffic within the traffic, that are separated based on distance to the victim-end network. For the traceback component, the existing Fast Internet Traceback (FIT) technique is employed to find remote edge routers which forward attack traffic to the victim. In the response component, the distance-based rate limit mechanism quickly lowers attack traffic by setting up rate limits on these routers. We evaluate the distance-based DDoS defense system on a network simulation platform called NS2. The results demonstrate that both detection techniques are capable of detecting flooding-based DDoS attacks, and the defense system can effectively control attack traffic to sustain quality of service for legitimate users. Moreover, the system shows better performance in defeating flooding-based DDoS attacks compared to the pushback technique which uses a local aggregate congestion control mechanism. / Thesis (Master, Computing) -- Queen's University, 2007-08-22 23:01:20.581

Planning device deployment is a fundamental issue in implementing wireless sensor network (WSN) applications. This design practice determines types, numbers and locations of devices in order to build a powerful and effective system using devices of limited energy supply and constrained capacities. The deployment plan decides the limits of many intrinsic properties of a WSN, such as coverage, connectivity, cost, and lifetime. In this thesis, we address the device deployment planning issues related to large-scale WSN systems. We consider a typical deployment planning scenario in a heterogeneous two-tier WSN composed of sensor nodes and relay nodes. Sensor nodes form the lower tier of the network and are responsible for providing satisfactory sensing coverage to the application. Relay nodes form the upper tier of the network and they are responsible for forwarding data from sensor nodes to the base station. As so, relay nodes should provide reliable connectivity to sensor nodes for an extended period of time. We therefore address the sensor node deployment in terms of the sensing coverage and relay node deployment in terms of the communication connectivity and system lifetime. For sensor node deployment, we propose a coverage-guaranteed sensor node deployment design technique. Using this technique, the sensing coverage is complete even if sensor nodes are randomly dispersed within a bounded range from its target locations according to a given grid pattern. In order to curb the increased cost due to extra sensor nodes that are used in the coverage-guaranteed deployment, while still maintaining a high-quality sensing coverage, we further study the probabilistic properties of the grid-based sensor node deployment in the presence of deployment errors. For relay node deployment, we propose to extend the system lifetime by distributing relay nodes according to a density function, which is optimized in response to the energy consumption rate, so that the energy is dissipated at an approximately same rate across the network. We further craft the deployment density function to reconcile the needs of balanced energy consumption and strong sensor node connectivity. The techniques proposed in this thesis fill the blank of available literature and can serve as guidelines for WSN designers, solution providers and system integrators of WSN applications. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-01-15 09:33:53.917

The scaling of VLSI technology has allowed extensive integration of processing resources on a single chip. Consequently, programmable chips is able to have a high logic and memory capacity for implementation of complex systems. Field-programmable gate arrays (FPGAs) with their embedded memory and other specialized functionality have become viable alternatives in many cases to costly application-specific integrated circuits as a system-on-chip (SoC) substrate. However, on-chip bus-based interconnects are no longer suitable for complex SoC design because of its limited scalability. The network-on-chip (NoC)paradigm has therefore emerged as a scalable approach for addressing this challenge. FPGAs can also adopt the NoC paradigm in order to support more complex SoC implementations. The elements for NoC support can be implemented in conventional programmable logic within an FPGA, however, a dedicated approach for these NoC elements can lead to better performance and more efficient utilization of on-chip FPGA resources. A fixed network topology can be a disadvantage in NoC platforms due to misalignment with application requirements. It is therefore desirable to incorporate a certain level of configurability even for embedded NoC support within an FPGA. This thesis presents the design and implementation of a configurable router intended as a dedicated embedded module for NoC support in an FPGA. The goal is to provide a general NoC infrastructure for the FPGA platform that balances trade-offs with regard to logic complexity, resource utilization, and flexibility. The configurable router provides flexibility in implementing a variety of network topologies with the convenience of a 3-bit input to the router for configuration. All of the necessary routing functionality for each topology is implemented in logic for performance and area efficiency. The overall router design provides general NoC support with reduced complexity, thereby achieving area efficiency and an adequate clock frequency for typical operation in conjunction with embedded soft processors. Synthesis results are presented at the router level in order to characterize the hardware overhead for implementations in programmable logic as well as standard-cell technology, and at the system-level in order to evaluate overall system resource utilization. Operational results are shown at router level to demonstrate correctness and at system level to demonstrate functionality of the multiprocessor systems that utilizes the configurable router. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-24 23:24:01.907