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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Modeling Random Dopant Fluctuation Effects in Nanoscale Tri-gate FETs

Ogden, Joshua Lee 01 December 2011 (has links)
The tri-gate FET has been hailed as the biggest breakthrough in transistor technology in the last 20 years. The increase in device performance (faster switching, less delay, improved short channel effects, etc.) coupled with the reduction in device size, would allow for huge gains in the electronics industry. This thesis aims to not only investigate the validity of these claims, but also how random dopant fluctuation (RDF) affects the tri-gates performance and how to curb these issues. In order to achieve this, an atomistic 3-D device simulation program was utilized in order to capture the many quantum mechanical effects that devices of this size experience and compare the results against a similar planar device. We see the tri-gate FET does indeed perform extremely well compared to its planar counterpart, but both devices experience a great deal of fluctuations due to the random dopants in the device. In order to limit the RDF effects a variety of methods were implemented including increasing doping concentrations in the channel, source, and drain regions, varying the source/drain junction depths, and varying the source/drain contact workfunction. The results showed that increasing doping concentrations in order to reduce the amount of space the dopants had to diffuse did not reduce the randomness experienced by the devices, but rather the randomness increased. The dopant fluctuation was insensitive to the varying of the workfunction, but was found to decrease with an increase in junction depth in the source/drain regions. With randomness in the tri-gate reduced, the overall performance should increase when used in ICs, where consistency in device characteristics is essential.

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