This thesis presents two experimental microelectronic prototypes for neurophysiological applications. Both systems target diagnostics and treatment of neurological disorders, and they are experimentally validated in vivo by online intracranial EEG recording in freely moving rats. The first prototype is a 56-channel chopper-stabilized low-noise neural recording interface IC with programmable mixed-signal DC cancellation feedback, fabricated in a 0.13μm CMOS process. Each recording channel has a low-noise fully-differential amplifier, and a digital integrator and a delta-sigma DAC in the feedback to cancel DC offsets of up to ±50mV. Chopper stabilization technique is used to reduce the amplifier flicker noise. The recorded signals are digitized by 7 column-parallel SAR ADCs. The second prototype is a compact headset for multi-site neuromonitoring and neurostimulation in rodent brain. A stack of 2 mini-PCBs was designed and experimentally validated. It includes a previously fabricated 0.35μm CMOS recording and stimulation IC, a low-power FPGA, and the IC peripherals.

This thesis presents two experimental microelectronic prototypes for neurophysiological applications. Both systems target diagnostics and treatment of neurological disorders, and they are experimentally validated in vivo by online intracranial EEG recording in freely moving rats. The first prototype is a 56-channel chopper-stabilized low-noise neural recording interface IC with programmable mixed-signal DC cancellation feedback, fabricated in a 0.13μm CMOS process. Each recording channel has a low-noise fully-differential amplifier, and a digital integrator and a delta-sigma DAC in the feedback to cancel DC offsets of up to ±50mV. Chopper stabilization technique is used to reduce the amplifier flicker noise. The recorded signals are digitized by 7 column-parallel SAR ADCs. The second prototype is a compact headset for multi-site neuromonitoring and neurostimulation in rodent brain. A stack of 2 mini-PCBs was designed and experimentally validated. It includes a previously fabricated 0.35μm CMOS recording and stimulation IC, a low-power FPGA, and the IC peripherals.