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Jiang, Li. / "October 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 71-76). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Three Dimensional Integrated Circuit --- p.1 / Chapter 1.1.1 --- 3D ICs --- p.1 / Chapter 1.1.2 --- Manufacture --- p.3 / Chapter 1.2 --- Test Architecture Design and Optimization for SoCs --- p.4 / Chapter 1.2.1 --- Test Wrapper --- p.4 / Chapter 1.2.2 --- Test Access Mechanism --- p.6 / Chapter 1.2.3 --- Test Architecture Optimization and Test Scheduling --- p.7 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 2 --- On Test Time and Routing Cost --- p.12 / Chapter 2.1 --- Introduction --- p.12 / Chapter 2.2 --- Preliminaries and Motivation --- p.13 / Chapter 2.3 --- Problem Formulation --- p.17 / Chapter 2.3.1 --- Test Cost Model --- p.17 / Chapter 2.3.2 --- Routing Model --- p.17 / Chapter 2.3.3 --- Problem Definition --- p.19 / Chapter 2.4 --- Proposed Algorithm --- p.22 / Chapter 2.4.1 --- Outline of The Proposed Algorithm --- p.22 / Chapter 2.4.2 --- SA-Based Core Assignment --- p.24 / Chapter 2.4.3 --- Heuristic-Based TAM Width Allocation --- p.25 / Chapter 2.4.4 --- Fast routing Heuristic --- p.28 / Chapter 2.5 --- Experiments --- p.29 / Chapter 2.5.1 --- Experimental Setup --- p.29 / Chapter 2.5.2 --- Experimental Results --- p.31 / Chapter 2.6 --- Conclusion --- p.34 / Chapter 3 --- Pre-bond-Test-Pin Constrained Test Wire Sharing --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Preliminaries and Motivation --- p.38 / Chapter 3.2.1 --- Prior Work in SoC Testing --- p.38 / Chapter 3.2.2 --- Prior Work in Testing 3D ICs --- p.39 / Chapter 3.2.3 --- Test-Pin-Count Constraint in 3D IC Pre-Bond Testing --- p.40 / Chapter 3.2.4 --- Motivation --- p.41 / Chapter 3.3 --- Problem Formulation --- p.43 / Chapter 3.3.1 --- Test Architecture Design under Pre-Bond Test-Pin-Count Constraint --- p.44 / Chapter 3.3.2 --- Thermal-aware Test Scheduling for Post-Bond Test --- p.45 / Chapter 3.4 --- Layout-Driven Test Architecture Design and Optimization --- p.46 / Chapter 3.4.1 --- Scheme 1: TAM Wire Reuse with Fixed Test Architectures --- p.46 / Chapter 3.4.2 --- Scheme 2: TAM Wire Reuse with Flexible Pre-bond Test Architecture --- p.52 / Chapter 3.5 --- Thermal-Aware Test Scheduling for Post-Bond Test --- p.53 / Chapter 3.5.1 --- Thermal Cost Function --- p.54 / Chapter 3.5.2 --- Test Scheduling Algorithm --- p.55 / Chapter 3.6 --- Experimental Results --- p.56 / Chapter 3.6.1 --- Experimental Setup --- p.56 / Chapter 3.6.2 --- Results and Discussion --- p.58 / Chapter 3.7 --- Conclusion --- p.59 / Chapter 3.8 --- Acknowledgement --- p.60 / Chapter 4 --- Conclusion and Future Work --- p.69 / Bibliography --- p.70

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions. / Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.

FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements. / A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test. / An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.

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Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.