Master of Science

The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 500KHz from the 2.11GHz carrier, the measured phase noise is -101.9dBc/Hz for the NMOS oscillator with a power dissipation of 12.5mW. The complementary oscillator has a phase noise of -103.6dBc/Hz at 500KHz offset from the 2.19GHz carrier and a power dissipation of 6.25mW from a 2.5V power supply. A wide tuning range of 16% is obtained by means of a PMOS varactor in conjunction with an array of switched capacitors. / Graduation date: 2002

by Cheuk-Him, To. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / Abstract also in Chinese. / ACKNOWLEDGMENT --- p.I / ABSTRACT (ENGLISH) --- p.II / ABSTRACT (CHINESE) --- p.III / CONTENTS --- p.IV / TABLE OF FIGURES --- p.VI / Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Different types of DCO --- p.1-2 / Chapter 1.2.1 --- Divided by N counter --- p.1-2 / Chapter 1.2.2 --- Increment-decrement counter --- p.1-2 / Chapter 1.2.3 --- Controlled delay ring oscillator --- p.1-4 / Chapter 1.3 --- Problems suffered from these circuits --- p.1-4 / Chapter 1.4 --- Characteristics of the proposed circuit --- p.1-5 / Chapter CHAPTER 2 --- BACKGROUND THEORY --- p.2-1 / Chapter 2.1 --- Ring Oscillator --- p.2-1 / Chapter 2.2 --- Differential Pair --- p.2-1 / Chapter 2.3 --- Injection Locked Oscillator (ILO) --- p.2-2 / Chapter 2.4 --- Digital Controlled Oscillator --- p.2-3 / Chapter CHAPTER 3 --- DESIGN --- p.3-1 / Chapter 3.1 --- Circuit Description --- p.3-1 / Chapter 3.1.1 --- D/A converter --- p.3-2 / Chapter 3.1.2 --- Injection Locked Oscillator (ILO) --- p.3-3 / Chapter 3.2 --- Design Characteristics --- p.3-5 / Chapter 3.2.1 --- D/A converter --- p.3-5 / Chapter 3.2.2 --- ILO --- p.3-7 / Chapter 3.2.3 --- Physical Design (Layout Drawing) --- p.3-8 / Chapter CHAPTER 4 --- RESULTS --- p.4-1 / Chapter 4.1 --- Chip1 --- p.4-1 / Chapter 4.1.1 --- Simulation --- p.4-3 / Chapter 4.1.2 --- Measurement --- p.4-15 / Chapter 4.1.3 --- Evaluation --- p.4-23 / Chapter 4.2 --- Chip2 --- p.4-25 / Chapter 4.2.1 --- Simulation --- p.4-25 / Chapter 4.2.2 --- Measurement --- p.4-36 / Chapter 4.2.3 --- Evaluation --- p.4-47 / Chapter CHAPTER 5 --- CONCLUSION --- p.5-1 / REFERENCES: --- p.1 / APPENDIX: --- p.1

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.05𝑚𝑚2 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net 𝐹𝑂𝑀𝐴 of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is > 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator.

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis.

Graduation date: 2001

E.E. David, Jr. / "August 30, 1948." / Army Signal Corps Contract No. W-36-039 sc-32037 Project No. 102B. Dept. of the Army Project No. 3-99-10-022.

R.R. Moats. / "This report is essentially the same as a doctoral thesis in the Department of Electrical Engineering, M.I.T." "June 25, 1951." / Bibliography: p. 53-54. / Army Signal Corps Contract No. DA36-039 sc-100 Project No. 8-102B-0." Dept. of the Army Project No. 3-99-10-022.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 65-69).

Oscillator circuits are an integral component of wireless communications systems and are increasingly in demand. As such systems gain widespread use, price becomes a very important factor in the design process, and the design cycle must be optimized. This puts an increasing emphasis on the proficiency of oscillator design automation tools. At the same time, as the performance requirements of such systems are becoming more stringent, the required simulation complexity is also increasing. More specifically, high frequency selectivity and low phase noise require very high quality factor oscillators, which in turn negatively affect the convergence performance of current simulation techniques. This thesis proposes a new continuation method for improving the convergence of oscillator simulations and compares this method to some of the methods reported in the literature. The proposed approach does not require a very good initial guess in order to converge to a final solution.