Chip scale refrigeration system is critical for the development of electronics with the rapid increase of power consumption and substantial reduction of device size, resulting in an emergent demand on novel cooling technologies with a high efficiency for the thermal management. In this thesis, active refrigeration devices based on Stirling cycle and an electrocaloric material, are designed and investigated to achieve a high cooling performance. Firstly, a new Stirling micro-refrigeration system composed of arrays of silicon MEMS cooling elements is designed and evaluated. The cooling elements are fabricated in a stacked array on a silicon wafer. A regenerator is placed between the compression (hot side) and expansion (cold side) diaphragms, which are driven electrostatically. Under operating conditions, the hot and cold diaphragms oscillate sinusoidally and out of phase such that heat is extracted to the expansion space and released from the compression space. A first-order of thermodynamic analysis is performed to study the effect of geometric parameters. Losses due to regenerator non-idealities and chamber heat transfer limitation are estimated. A multiphysics computational approach for analyzing the system performance that considers compressible flow and heat transfer with a large deformable mesh is demonstrated. The optimal regenerator porosity for the best system COP (coefficient of performance) is identified. To overcome the computational complexity brought about by the fine pillar structure in the regenerator, a porous medium model is used to allow for modeling of a full element. The analysis indicates the work recovery of the system and the diaphragm actuation are main challenges for this cooler design.The pressure drop and friction factor of gas flow across circular silicon micro pillar arrays fabricated by deep reactive ion etch (DRIE) process are investigated. A new correlation that considers the coupled effect of pillar spacing and aspect ratio, is proposed to predict the friction factor in a Reynolds v number range of 1-100. Silicon pillars with large artificial roughness amplitudes is also fabricated, and the effect of the roughness is studied in the laminar flow region. The significant reduction of pressure drop and friction factor indicates that a large artificial roughness could be built for pillar arrays in the regenerator to enhance the micro-cooler efficiency. The second option is to develop a fluid-based refrigeration system using an electrocaloric material poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene) [P(VDF-TrFE-CFE)] terpolymer. Each cooling element includes two diaphragm actuators fabricated in the plane of a silicon wafer, which drive a heat transfer fluid back and forth across terpolymer layers that are placed between them. Finite element simulations with an assumption of sinusoidal diaphrahm motions are conducted to explore the system performance detailedly, including the effects of the applied electric field, geometric dimensions, operating frequency and externally-applied temperature span. Multiphysics modeling coupled with solid-fluid interaction, heat transfer, electrostatics, porous medium and moving mesh technique is successfully performed to verify the thermal modeling feasibility. The electrocaloric effect in thin films of P(VDF-TrFE-CFE) terpolymer is directly measured by infrared imaging at ambient conditions. At an electric field of 90 V/μm, an adiabatic temperature change of 5.2 °C is obtained and the material performance is stable over a long testing period. These results suggest that application of this terpolymer is promising for micro-scale refrigeration.

Esta tese tem por objetivo o desenvolvimento de metodologias eficientes e de baixo custo para ajustar as propriedades elétricas de OFETs de canal p e de canal n, a fim de possibilitar a fabricação do circuito complementar orgânico, semelhante a uma estrutura CMOS. O desempenho do circuito complementar fabricado foi otimizado, e também foi confeccionado por impressão um OFETs de canal operando em baixas tensões. Para a fabricação do CMOS orgânico foi proposto um método baseado na seleção adequada do solvente da camada dielétrica para ajustar o desempenho elétrico dos OFETs de canal p e de canal n. Os solventes, MEK, nBA e DMSO foram selecionados para a dissolução do PMMA por apresentarem diferenças nos valores de momento de dipolo, de ponto de ebulição e de graus de ortogonalidade em relação as camadas semicondutoras de P3HT e de P(NDI2OD-T2) dos OFETs. A análise dos resultados dos OFETs de canal p e de canal n demonstrou que a metodologia proposta é adequada tanto para o ajuste das propriedades elétricas destes dispositivos quanto para a otimização do desempenho dos mesmos. Os melhores desempenhos elétricos para os OFETs de canal p e de canal n foram obtidos quando utilizados o DMSO e o MEK como solventes do PMMA, respectivamente, devido à perfeita ortogonalidade destes solventes em relação às camadas semicondutoras. Os OFETs de canal p que utilizaram o DMSO e os OFETs de canal n que utilizaram o nBA foram os que apresentaram desempenhos elétricos semelhantes, sendo portanto aplicados na fabricação do CMOS. Valores de ganho entre 6,8 e 7,8 e de margem de ruído entre 28,3 V e 34,5 V foram obtidos para inversores complementares fabricados nesta etapa do trabalho. OFETs de canal p utilizando uma blenda de PTAA: diF TES ADT como camada semicondutora, o PEDOT:PSS como eletrodos dreno/fonte e o P(VDF-TrFE-CFE) como camada dielétrica também foram fabricados neste trabalho. A técnica de blade-coating foi utilizada para a deposição dos eletrodos dreno/fonte e da camada semicondutora, ao passo que a técnica de spray-coating foi utilizada para a deposição da camada dielétrica. Da análise dos resultados foi possível inferir que a utilização de um dielétrico com elevada constante dielétrica (K), como o P(VDF-TrFE-CFE), possibilita o funcionamento dos transistores a baixas tensões (≤ 8 V), porém com valores de mobilidade reduzidos devido à elevada desordem dipolar na interface provocada por este dielétrico. Para minimizar esses efeitos, uma fina camada de um polímero fluorado foi depositada entre a camada semicondutora e a dielétrica pela técnica de blade-coating, constituindo assim uma bicamada dielétrica nos OFETs. Dos resultados das medidas elétricas dos OFETs constituídos pela bicamada dielétrica foi observada permanência do funcionamento destes dispositivos a tensões inferiores a 8 V com desempenho elétricos superiores a resultados já publicados na literatura. Por fim, inversores lógicos unipolares com transistores de carga foram fabricados com os OFETs que utilizaram a bicamada dielétrica, sendo obtidos valores de ganho entre 1,2 e 1,6 e de margem de ruído entre 56% e 68,5% de ½ VDD. / This thesis aimed to develop an efficient and low cost method to adjust the electrical properties of p- and n-channel OFETs to allow us to build an organic CMOS and the optimization of printed p-channel OFETs to work at low voltages. We proposed a method to fabricate the organic CMOS, based on the careful selection of dielectric solvent, which was adjusted to obtain the best performance of p- and n-channel OFETs. The dielectric solvents as MEK, nBA and DMSO were selected to dissolve the PMMA dielectric polymer due their different physical properties as dipole moment and boiling point and because they showed slightly different degrees of orthogonality to the P3HT and P(NDI2OD-T2) semiconductor layers of the OFETs. The results showed that the careful selection of the dielectric solvent not only allows to tune the electrical characteristics of the p- and n-channel OFETs, but also to improve the performance of these devices. The best performances were achieved when DMSO and MEK were used as dielectric solvents of the p and n-channel OFETs, respectively, as result of the perfectly orthogonality of these solvents to the semiconductor layers. P-channel OFETs using DMSO and n-channel OFETs using nBA showed similar electrical characteristics and thus, they were used to construct the organic CMOS. The organic complementary inverters showed high gain and noise margin values in the range of 6,8 to 7,8 and 28,3 V to 34,5 V, respectively. Printed p-channel OFETs were also fabricated, in which the blend PTAA:diF TES ADT was used as semiconductor channel, PEDOT:PSS as the drain/source electrodes and P(VDF-TrFE-CFE) as the dielectric layer. The blade-coating technique was used to deposit the source/drain electrodes and the semiconductor layer, while the spray-coating technique was used to deposit the dielectric layer. It was observed that using high-k dielectric as P(VDF-TrFE-CFE) enable to reduce the operating voltage of the OFETs (≤8 V), however, this high-k dielectric also reduced the field effect mobility due the dipolar disorder at the semiconductor/dielectric interface. To minimize the dipolar issue at the interface, we inserted a thin fluoropolymer dielectric layer by blade-coating between the semiconductor and the high-k dielectric layers, thus constituting a dielectric bilayer on the OFETs. From the electrical measurements of the OFETs with the dielectric bilayer, it was observed that the devices were still working at 8 V and they also showed better performance in comparison to results already published. Finally, organic unipolar inverters with load transistors were fabricated using the p-channel OFETs with the dielectric bilayer and they showed reasonable performance, with gain and noise margin in the range of 1,2 to 1,6 and 56% e 68,5% of ½ VDD, respectively.

Esta tese tem por objetivo o desenvolvimento de metodologias eficientes e de baixo custo para ajustar as propriedades elétricas de OFETs de canal p e de canal n, a fim de possibilitar a fabricação do circuito complementar orgânico, semelhante a uma estrutura CMOS. O desempenho do circuito complementar fabricado foi otimizado, e também foi confeccionado por impressão um OFETs de canal operando em baixas tensões. Para a fabricação do CMOS orgânico foi proposto um método baseado na seleção adequada do solvente da camada dielétrica para ajustar o desempenho elétrico dos OFETs de canal p e de canal n. Os solventes, MEK, nBA e DMSO foram selecionados para a dissolução do PMMA por apresentarem diferenças nos valores de momento de dipolo, de ponto de ebulição e de graus de ortogonalidade em relação as camadas semicondutoras de P3HT e de P(NDI2OD-T2) dos OFETs. A análise dos resultados dos OFETs de canal p e de canal n demonstrou que a metodologia proposta é adequada tanto para o ajuste das propriedades elétricas destes dispositivos quanto para a otimização do desempenho dos mesmos. Os melhores desempenhos elétricos para os OFETs de canal p e de canal n foram obtidos quando utilizados o DMSO e o MEK como solventes do PMMA, respectivamente, devido à perfeita ortogonalidade destes solventes em relação às camadas semicondutoras. Os OFETs de canal p que utilizaram o DMSO e os OFETs de canal n que utilizaram o nBA foram os que apresentaram desempenhos elétricos semelhantes, sendo portanto aplicados na fabricação do CMOS. Valores de ganho entre 6,8 e 7,8 e de margem de ruído entre 28,3 V e 34,5 V foram obtidos para inversores complementares fabricados nesta etapa do trabalho. OFETs de canal p utilizando uma blenda de PTAA: diF TES ADT como camada semicondutora, o PEDOT:PSS como eletrodos dreno/fonte e o P(VDF-TrFE-CFE) como camada dielétrica também foram fabricados neste trabalho. A técnica de blade-coating foi utilizada para a deposição dos eletrodos dreno/fonte e da camada semicondutora, ao passo que a técnica de spray-coating foi utilizada para a deposição da camada dielétrica. Da análise dos resultados foi possível inferir que a utilização de um dielétrico com elevada constante dielétrica (K), como o P(VDF-TrFE-CFE), possibilita o funcionamento dos transistores a baixas tensões (≤ 8 V), porém com valores de mobilidade reduzidos devido à elevada desordem dipolar na interface provocada por este dielétrico. Para minimizar esses efeitos, uma fina camada de um polímero fluorado foi depositada entre a camada semicondutora e a dielétrica pela técnica de blade-coating, constituindo assim uma bicamada dielétrica nos OFETs. Dos resultados das medidas elétricas dos OFETs constituídos pela bicamada dielétrica foi observada permanência do funcionamento destes dispositivos a tensões inferiores a 8 V com desempenho elétricos superiores a resultados já publicados na literatura. Por fim, inversores lógicos unipolares com transistores de carga foram fabricados com os OFETs que utilizaram a bicamada dielétrica, sendo obtidos valores de ganho entre 1,2 e 1,6 e de margem de ruído entre 56% e 68,5% de ½ VDD. / This thesis aimed to develop an efficient and low cost method to adjust the electrical properties of p- and n-channel OFETs to allow us to build an organic CMOS and the optimization of printed p-channel OFETs to work at low voltages. We proposed a method to fabricate the organic CMOS, based on the careful selection of dielectric solvent, which was adjusted to obtain the best performance of p- and n-channel OFETs. The dielectric solvents as MEK, nBA and DMSO were selected to dissolve the PMMA dielectric polymer due their different physical properties as dipole moment and boiling point and because they showed slightly different degrees of orthogonality to the P3HT and P(NDI2OD-T2) semiconductor layers of the OFETs. The results showed that the careful selection of the dielectric solvent not only allows to tune the electrical characteristics of the p- and n-channel OFETs, but also to improve the performance of these devices. The best performances were achieved when DMSO and MEK were used as dielectric solvents of the p and n-channel OFETs, respectively, as result of the perfectly orthogonality of these solvents to the semiconductor layers. P-channel OFETs using DMSO and n-channel OFETs using nBA showed similar electrical characteristics and thus, they were used to construct the organic CMOS. The organic complementary inverters showed high gain and noise margin values in the range of 6,8 to 7,8 and 28,3 V to 34,5 V, respectively. Printed p-channel OFETs were also fabricated, in which the blend PTAA:diF TES ADT was used as semiconductor channel, PEDOT:PSS as the drain/source electrodes and P(VDF-TrFE-CFE) as the dielectric layer. The blade-coating technique was used to deposit the source/drain electrodes and the semiconductor layer, while the spray-coating technique was used to deposit the dielectric layer. It was observed that using high-k dielectric as P(VDF-TrFE-CFE) enable to reduce the operating voltage of the OFETs (≤8 V), however, this high-k dielectric also reduced the field effect mobility due the dipolar disorder at the semiconductor/dielectric interface. To minimize the dipolar issue at the interface, we inserted a thin fluoropolymer dielectric layer by blade-coating between the semiconductor and the high-k dielectric layers, thus constituting a dielectric bilayer on the OFETs. From the electrical measurements of the OFETs with the dielectric bilayer, it was observed that the devices were still working at 8 V and they also showed better performance in comparison to results already published. Finally, organic unipolar inverters with load transistors were fabricated using the p-channel OFETs with the dielectric bilayer and they showed reasonable performance, with gain and noise margin in the range of 1,2 to 1,6 and 56% e 68,5% of ½ VDD, respectively.

Les recherches que nous présentons dans ce mémoire s'inscrivent dans le cadre du développement de nouvelles structures et de l'étude de matériaux accordables en vue d'une intégration industrielle comme radôme actif.Plus particulièrement, ils consistent en la réalisation d'un dispositif micro-onde permettant à la fois un filtrage et une agilité fréquentiels en espace libre. Des structures basées sur des surfaces sélectives en fréquences, pour l'aspect filtrage, et sur des matériaux de type ferroélectrique, pour l'aspect accordabilité, sont développées. Des modélisations et des simulations électromagnétiques montrent que le changement de permittivité du matériau, obtenu par application d'un champ électrique externe, permet le pilotage fréquentiel de la transmission de la structure. Une mise en oeuvre expérimentale complète ces travaux, au cours de laquelle des prototypes ont été fabriqués par des techniques de photolithographie, puis caractérisés en espace libre grâce à un banc ABmm. Les mesures micro-ondes valident ainsi les résultats de simulations menées en amont et montrent les possibilités de contrôler la fréquence de transmission du radôme. / The research we present in this memory registers within the framework to develop new structures and to study tunable materials for an industrial integration as an active radome. Specifically, they consist of achieving a free space microwave device for both a filtering behaviour and a frequency agility behaviour. Structures based on frequency selective surfaces, for the filtering aspect, and on ferroelectric materials for the tuning aspect, are developed. Modeling and simulations show that the change of the material permittivity, obtained by applying an external electric field, enable piloting the transmission frequency of the structure. An experimental implementation complete this work and prototypes have been fabricated by photolithography techniques and then characterized in free space with a bench ABmm. Thus, microwave measurements validate the results of simulations and show the possibility to control the frequency transmission of the radome.