Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Jeannine Mosely. / M.S.

by Xu Haoyu. / Thesis submitted in: July 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 89-95). / Abstracts in English and Chinese. / Acknowledgement --- p.i / Abstract --- p.ii / 摘要 --- p.iii / Contents --- p.iv / List of Abbreviations --- p.vii / List of Tables --- p.viii / List of Figures --- p.ix / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.2 / Chapter 1.1.1 --- Routing --- p.2 / Chapter 1.1.2 --- Ant Colony Optimization --- p.6 / Chapter 1.2 --- Research Statement --- p.8 / Chapter 1.3 --- Main Contributions --- p.10 / Chapter 1.4 --- Thesis Organization --- p.11 / Chapter Chapter 2 --- Ant Colony Optimization Routing --- p.12 / Chapter 2.1 --- ACO Routing Algorithms --- p.13 / Chapter 2.1.1 --- ACO Routing Algorithms in Circuit-Switched Networks --- p.13 / Chapter 2.1.2 --- ACO Routing Approaches in Packet-Switched Networks --- p.16 / Chapter 2.2 --- ACO Routing and Traditional Routing Algorithms --- p.23 / Chapter 2.3 --- ACO Routing and Optimal Routing Algorithms --- p.26 / Chapter Chapter 3 --- Reactive Ant Colony Optimization --- p.31 / Chapter 3.1 --- Problem Model --- p.31 / Chapter 3.2 --- RACO Routing Approach --- p.35 / Chapter 3.2.1. --- Node and Probabilistic Routing Table --- p.36 / Chapter 3.2.2. --- Ants --- p.38 / Chapter 3.2.3 --- Detailed Description of RACO routing approach --- p.43 / Chapter Chapter 4 --- Simulation Results --- p.45 / Chapter 4.1 --- Experiment Design --- p.45 / Chapter 4.1.1 --- Topology --- p.46 / Chapter 4.1.2 --- Network Layers --- p.48 / Chapter 4.2 --- Results --- p.50 / Chapter 4.2.1 --- NSFNET --- p.50 / Chapter 4.2.2 --- ARPANET --- p.52 / Chapter 4.3 --- Discussion --- p.53 / Chapter Chapter 5 --- Convergence Analysis --- p.58 / Chapter 5.1. --- Related Work --- p.59 / Chapter 5.2 --- "Two-Node, Two-Path Model" --- p.61 / Chapter 5.3 --- The Recursive Pheromone Values --- p.64 / Chapter 5.4 --- Pheromone Convergence --- p.70 / Chapter 5.5 --- General Models --- p.81 / Chapter 5.5.1 --- "Two - Node, N - Path Model" --- p.81 / Chapter 5.5.2 --- "M- Node, N(i.j) - Path Model" --- p.83 / Chapter 5.6. --- Conclusion and Discussion --- p.84 / Chapter Chapter 6 --- Conclusion and Future Work --- p.86 / Chapter 6.1 --- Conclusion --- p.86 / Chapter 6.2 --- Future Work --- p.87 / Reference --- p.89 / Appendices --- p.96 / "Appendix 1 The Detailed Form of P = f1（a,b) and Q = f2（a,b)" --- p.96 / "Appendix 2 To Validate Whether f1（a,b) in the Domain of (0,1)" --- p.102

Chow Chi Wai. / "July 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Recently, the Birkhoff-von Neumann (BvN) switch has become a typical model for providing QoS in input-queued switch. The major idea is to consider a set of predetermined permutation matrices as independent flows, and the scheduling problem in the input-queued switch can be simply handled by single-server scheduling algorithms, such as weighted fair queueing (WFQ). However, a number of problems are observed. Firstly, although WFQ is a fair algorithm, it has a poor delay performance that depends on the port counts. Secondly, the BvN switch does not perform well under certain traffic requirement, thus unable to provide tight performance guarantees. In this thesis, a set of admission control strategies and scheduling algorithms are therefore developed to improve the QoS performance. / The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high speeds. A central problem in designing an input-queued switch is choosing the scheduling algorithm, i.e. deciding which packets to transfer from input ports to output ports in a given timeslot. Recent research in packet switch scheduling algorithms has moved beyond throughput maximization to quality of service (QoS) control. / Choy Man Ting. / "September 2006." / Adviser: Tony T. Lee. / Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1815. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 89-94). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

by Philip Pak-tung To. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (p. 126). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

by Timothy Kai-Cheung Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references. / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 2. --- ASYNCHRONOUS TRANSFER MODE SWITCHING --- p.4 / Chapter 2.1 --- Transfer Modes --- p.4 / Chapter 2.1.1 --- Circuit Switching --- p.4 / Chapter 2.1.2 --- ATM Switching --- p.6 / Chapter 2.1.3 --- Packet Switching --- p.8 / Chapter 2.2 --- Different Types of ATM Switching System --- p.8 / Chapter 2.2.1 --- Central Control Type --- p.9 / Chapter 2.2.2 --- Self-Routing Type --- p.9 / Chapter 2.3 --- Self-Routing Non-Buffering ATM Switching Node --- p.10 / Chapter 3. --- FUNCTIONAL DESCRIPTION OF MODULE ´بA´ة --- p.16 / Chapter 3.1 --- ATM Cell Format --- p.17 / Chapter 3.2 --- Concentrator --- p.17 / Chapter 3.3 --- Routing Cell --- p.19 / Chapter 4. --- PHYSICAL STRUCTURE OF MODULE ´بA´ة --- p.23 / Chapter 4.1 --- Clocking Scheme --- p.23 / Chapter 4.2 --- Concentrator --- p.25 / Chapter 4.2.1 --- 2-by-2 Sorter --- p.25 / Chapter 4.2.2 --- Input Framer --- p.30 / Chapter 4.2.3 --- Data Buffer --- p.38 / Chapter 4.3 --- Routing Cell --- p.38 / Chapter 4.3.1 --- Type I Router --- p.39 / Chapter 4.3.2 --- Type II Router --- p.42 / Chapter 4.4 --- Block By-Passed Function --- p.43 / Chapter 5. --- SIMULATION AND TEST --- p.48 / Chapter 5.1 --- Computer Simulation --- p.48 / Chapter 5.2 --- Actual Chip Testing --- p.53 / Chapter 5.3 --- Measurement Results --- p.55 / Chapter 5.3.1 --- Functionality --- p.55 / Chapter 5.3.2 --- Maximum Clock Frequency --- p.60 / Chapter 5.3.3 --- Power Dissipation --- p.61 / Chapter 6. --- CONCLUSION --- p.63 / Chapter A. --- BRIEF HISTORY OF ATM SWITCH ARCHITECTURE DEVELOPMENT --- p.65 / Chapter B. --- BIBLIOGRAPHY --- p.66 / Chapter C. --- A N-WELL CMOS PROCESS --- p.70 / Chapter D. --- CADENCE DESIGN FLOW --- p.73 / Chapter E. --- YERILOG SIMULATION PROGRAMS --- p.77 / Chapter F. --- SCHEMATIC DIAGRAMS --- p.100

Choy Man Ting. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 66-69). / Abstracts in English and Chinese. / Acknowledgments --- p.ii / Abstract --- p.v / Table of Contents --- p.vii / List of figures --- p.viii / Chapter Chapter 1 --- p.12 / Chapter 1.1 --- OBS Network Architecture --- p.3 / Chapter 1.2 --- Offset Time and Reservation Schemes --- p.5 / Chapter 1.3 --- Research Objectives --- p.7 / Chapter 1.4 --- Overview --- p.8 / Chapter Chapter 2 --- p.9 / Chapter 2.1 --- WDM crossbar architectures --- p.9 / Chapter 2.2 --- Switch Based on Optical Crossbars --- p.10 / Chapter 2.3 --- Switch Based on Wavelength Grating Routers --- p.11 / Chapter Chapter 3 --- p.14 / Chapter 3.1 --- Basics of Dual Shuffle Exchange Network --- p.14 / Chapter 3.2 --- Dual Shuffle-exchange Network --- p.16 / Chapter 3.3 --- Proposed Architecture based on DSN --- p.19 / Chapter 3.4 --- Analysis on blocking due to output contention --- p.20 / Chapter 3.5 --- Implementation issues on the 4x4 switching module --- p.23 / Chapter 3.6 --- Analysis: Non-blocking versus banyan --- p.25 / Chapter Chapter 4 --- p.30 / Chapter 4.1 --- First Scheme --- p.30 / Chapter 4.2 --- Simulation on the first scheme --- p.33 / Chapter 4.3 --- Second Scheme: Tunable wavelength converter --- p.37 / Chapter 4.4 --- Third Scheme: Route to specific wavelength port --- p.42 / Chapter 4.5 --- Analysis on blocking due to insufficient stages --- p.46 / Chapter Chapter 5 --- p.49 / Chapter 5.1 --- Delay analysis of DSN --- p.49 / Chapter 5.2 --- Vertical Expansion --- p.51 / Chapter 5.3 --- Simulation results on vertical expansion --- p.52 / Chapter 5.4 --- Building DSN with 8x8 MEMS switches --- p.54 / Chapter 5.5 --- Prove of the proposed Quarter shuffle network --- p.56 / Chapter 5.6 --- Comparison between Quarter shuffle and doubled links approaches --- p.58 / Chapter Chapter 6 --- p.64 / Conclusion --- p.64 / Bibliography --- p.66

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaf 73. / by Oliver Chukwudi Ibe. / M.S.

Moshe Sidi and Adrian Segall. / Bibliography: p. 17. / "June, 1981." / Office of Naval Research contract No. ONR/N00014-77-C-0532

Michael G. Hluchyj and Robert G. Gallager. / Bibliography: leaf 7. / Caption title. "August, 1981." / DARPA Contract ONR no. N00014-75-C-1183 Program Code no. 5T10 ONR Identifying no. 049-383