The motivation of the research presented in this thesis is to investigate image processing algorithms utilising various SIMD parallel devices, especially massively parallel Cellular Processor Arrays (CPAs), to accelerate their processing speed. Various SIMD processors with different architectures are reviewed, and their features are analysed. The different types of parallelisms contained in image processing tasks are also analysed, and the methodologies to exploit date-level parallelisms are discussed. The efficiency of the pixel-per-processor architecture used in computer vision scenarios are discussed, as well as its limitations. Aiming to solve the problem that CPA array dimensions are usually smaller than the resolution of the images needed to be processed, a “coarse grain mapping method” is proposed. It provides the CPAs with the ability of processing images with higher resolution than the arrays themselves by allowing CPAs to process multiple pixels per processing element. It is completely software based, easy to implement, and easy to program. To demonstrate the efficiency of pixel-level parallel approach, two image processing algorithms specially designed for pixel-per-processor arrays are proposed: a parallel skeletonization algorithm based on two-layer trigger-wave propagation, and a parallel background detection algorithm. Implementations of the proposed algorithms using different platforms (i.e. CPU, GPU and CPA) are proposed and evaluated. Evaluation results indicate that the proposed algorithms have advantages both in term of processing speed and result quality. This thesis concludes that pixel-per-processor architecture can be used in image processing (or computer vision) algorithms which emphasize analysing pixel-level information, to significantly boost the processing speed of these algorithms.

Smoothing filters have been extensively used for noise removal and image restoration. Directional filters are widely used in computer vision and image processing tasks such as motion analysis, edge detection, line parameter estimation and texture analysis. It is practically impossible to tune the filters to all possible positions and orientations in real time due to huge computation requirement. The efficient way is to design a few basis filters, and express the output of a directional filter as a weighted sum of the basis filter outputs. Directional filters having these properties are called "Steerable Filters." This thesis work emphasis is on the implementation of proposed computationally efficient separable and steerable Gaussian smoothers on a Xilinx VirtexII Pro FPGA platform. FPGAs are Field Programmable Gate Arrays which consist of a collection of logic blocks including lookup tables, flip flops and some amount of Random Access Memory. All blocks are wired together using an array of interconnects. The proposed technique [2] is implemented on a FPGA hardware taking the advantage of parallelism and pipelining.