Ao final desta pesquisa deseja-se que haja uma metodologia eficiente, cuja finalidade será auxiliar o usuário na transformação de modelos matemáticos e computacionais codificados para computadores sequenciais, em modelos paralelos otimizados para executarem em microcomputadores pessoais modernos, constituídos de CPU com múltiplos núcleos ou de híbridos (CPU + GPGPU) integrados no mesmo chip, com ou sem processadores gráficos (GPGPU) densamente paralelos instalados, mantendo a qualidade de seus resultados originais, com respeito à sua precisão numérica, mas com uma diminuição considerável no tempo de processamento. A emergência, em meados da década 2000, dessas novas arquiteturas de hardware elevou a capacidade de processamento dos microcomputadores pessoais aos patamares dos computadores de grande porte de apenas alguns anos atrás. Este trabalho de pesquisa apresenta duas metodologias, onde a primeira metodologia é composta de três partes e a segunda de duas partes. Somente a terceira parte da primeira metodologia é dependente de tecnologias de hardware. / At the end of this research project, an efficient methodology is expected with the purpose of assisting users in the processing of mathematical and computer models coded for sequential computers in parallel models that are optimized to run on modern personal computers, consisting of a CPU with multiple or hybrid (CPU + GPGPU) cores integrated into the same chip, with or without massively parallel graphics processors (GPGPU) installed. This will ensure the original quality of the results with respect to numerical accuracy, but with a considerable reduction in processing time. The emergence of these new hardware architectures in the mid-2000s increased the processing power of personal computers to the levels of mainframe computers from just a few years previously. This research work presents two methodologies, where the first methodology is composed of three parts and the second methodology is composed of two parts. Only the third part of the first methodology is dependent on hardware technologies.

Ao considerar um sistema distribuído composto por um conjunto de servidores, clientes e recursos, que caracterizam ambientes como grades ou nuvens computacionais, que oferecem um grande número de recursos distribuídos como CPUs ou máquinas virtuais, os quais são utilizados conjuntamente por diferentes tipos de aplicações, tem-se a necessidade de se ter uma solução para alocação destes recursos. O apoio à alocação dos recursos fornecidos por tais ambientes deve satisfazer todas as solicitações de recursos das aplicações, e fornecer respostas afirmativas para alocação eficiente de recursos, fazer justiça na alocação no caso de pedidos simultâneos entre vários clientes de recursos e responder em um tempo finito a requisições. Considerando tal contexto de grande escala em sistemas distribuídos, este trabalho propõe um algoritmo distribuído para alocação de recursos. Este algoritmo explora a Lógica Fuzzy sempre que um servidor está impossibilitado de atender a uma solicitação feita por um cliente, encaminhando esta solicitação a um servidor remoto. O algoritmo utiliza o conceito de relógio lógico para garantir justiça no atendimento das solicitações feitas em todos os servidores que compartilham recursos. Este algoritmo segue o modelo distribuído, onde uma cópia do algoritmo é executada em cada servidor que compartilha recursos para seus clientes, e todos os servidores tomam parte das decisões com relação a alocação destes recursos. A estratégia desenvolvida tem como objetivo minimizar o tempo de resposta na alocação de recursos, funcionando como um balanceamento de carga em um ambiente cliente-servidor com alto índice de solicitações de recursos pelos clientes. A eficiência do algoritmo desenvolvido neste trabalho foi comprovada através da implementação e comparação com outros algoritmos tradicionais, mostrando a possibilidade de utilização de recursos que pertencem a distintos servidores por uma mesma solicitação de recursos, com a garantia de que esta requisição será atendida, e em um tempo finito. / When considering a distributed system composed of a set of servers, clients, and resources that characterize environments like computational grids or clouds that offer a large number of distributed resources such as CPUs or virtual machines, which are used jointly by different types of applications, there is the need to have a solution for allocating these resources. Support the allocation of resources provided by such environments must satisfy all Requests for resources such applications, and provide affirmative answers to the efficient allocation of resources, to do justice in this allocation in the case of simultaneous Requests from multiple clients and answer these resources in a finite time these Requests. Considering such a context of large- scale distributed systems, this paper proposes a distributed algorithm for resource allocation This algorithm exploits fuzzy logic whenever a server is unable to meet a request made by a client, forwarding this request to a remote server. The algorithm uses the concept of logical clock to ensure fairness in meeting the demands made on all servers that share resources. This algorithm follows a distributed model, where a copy of the algorithm runs on each server that shares resources for its clients and all servers take part in decisions regarding allocation of resources. The strategy developed aims to minimize the response time in allocating resources, functioning as a load-balancing in a client-server environment with high resource Requests by customers.

Orientador: Sérgio Azevedo de Oliveira / Banca: José Roberto Sanches Mantovani / Banca: Fujio Sato / Resumo: A metaheurística Busca Tabu, é uma técnica baseada em parâmetros de controle, a estrutura de vizinhança e seu próprio algoritmo com poderosas estratégias de busca. Nesta técnica, dada uma configuração, deseja-se passar ao melhor vizinho através da entrada e saída de ramos, obtendo assim a configuração incumbente. Com essa configuração que é considerada como a melhor configuração encontrada até o momento, e mesmo sendo um bom valor o sistema continua a busca procurando mais configurações até encontrar uma que seja melhor que as já encontradas até o momento. As versões paralelas dos algoritmos foram desenvolvidas a partir de um algoritmo BT serial avançado, sob o paradigma de programacão SPMD ("Single Program, Multiple Data"), e as mesmas foram testadas para sistemas testes de pequeno porte (Garver - 6 barras/15 ramos), médio porte (Sul brasileiro - 46 barras/79 ramos) e grande porte (Norte-Nordeste brasileiro - 87 barras/179 ramos) e seus resultados comparados com o resultado do algoritmo BT serial. Esta comparacão mostrou que os algoritmos propostos obtiveram um melhor desempenho, com alta eficiência. / Abstract: This paper deals with the use of Tabu Search metaheurístic applied to solving the problem of transmission system expansion planning (TSEP), analyzed on the static point of view, with the development of parallel algorithms in the environment MPI (?Message Passing Interface "). Tabu Search metaheurístic is a technique based on the control parameters, the structure of the neighborhood and its own algorithm with powerful search strategies. In this technique, given a configuration we want to progress to the best neighbor across the entrance and exit of branches, so getting the configuration incumbent. With this configuration which is regarded as the best configuration found so far, and this is a very good value, the system continuously seeking more settings to find a better than those found throughout the search. The parallel versions of the algorithms were developed from an advanced TS series algorithm on the paradigm of programming SPMD (Single Program Multiple Data), and they were tested for test systems small scale (Garver - bars 6/15 branches), medium scale (South Brazilian - 46 bars/79 branches) and large scale (North-Northeast Brazilian - 87 bars/179 branches), and their results compared with the result of the series algorithm TS. This comparison showed that the proposed algorithms obtained best performance and high efficiency. / Mestre

Ao final desta pesquisa deseja-se que haja uma metodologia eficiente, cuja finalidade será auxiliar o usuário na transformação de modelos matemáticos e computacionais codificados para computadores sequenciais, em modelos paralelos otimizados para executarem em microcomputadores pessoais modernos, constituídos de CPU com múltiplos núcleos ou de híbridos (CPU + GPGPU) integrados no mesmo chip, com ou sem processadores gráficos (GPGPU) densamente paralelos instalados, mantendo a qualidade de seus resultados originais, com respeito à sua precisão numérica, mas com uma diminuição considerável no tempo de processamento. A emergência, em meados da década 2000, dessas novas arquiteturas de hardware elevou a capacidade de processamento dos microcomputadores pessoais aos patamares dos computadores de grande porte de apenas alguns anos atrás. Este trabalho de pesquisa apresenta duas metodologias, onde a primeira metodologia é composta de três partes e a segunda de duas partes. Somente a terceira parte da primeira metodologia é dependente de tecnologias de hardware. / At the end of this research project, an efficient methodology is expected with the purpose of assisting users in the processing of mathematical and computer models coded for sequential computers in parallel models that are optimized to run on modern personal computers, consisting of a CPU with multiple or hybrid (CPU + GPGPU) cores integrated into the same chip, with or without massively parallel graphics processors (GPGPU) installed. This will ensure the original quality of the results with respect to numerical accuracy, but with a considerable reduction in processing time. The emergence of these new hardware architectures in the mid-2000s increased the processing power of personal computers to the levels of mainframe computers from just a few years previously. This research work presents two methodologies, where the first methodology is composed of three parts and the second methodology is composed of two parts. Only the third part of the first methodology is dependent on hardware technologies.

Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.

La loi de Moore sur semi-conducteurs approche de sa fin. L'evolution de l'architecture de von Neumann à travers les 40 ans d'histoire du microprocesseur a conduit à des circuits d'une insoutenable complexité, à un très faible rendement de calcul par transistor, et une forte consommation énergetique. D'autre-part, le monde du calcul parallèle ne supporte pas la comparaison avec les niveaux de portabilité, d'accessibilité, de productivité et de fiabilité de l'ingénérie du logiciel séquentiel. Ce dangereux fossé se traduit par des défis passionnants pour la recherche en compilation et en langages de programmation pour le calcul à hautes performances, généraliste ou embarqué. Cette thèse motive notre piste pour relever ces défis, introduit nos principales directions de travail, et établit des perspectives de recherche.

<p>Synthetic antenna aperture (SAR) is a pulses focusing airborne radar which can achieve high resolution radar image. A number of image process algorithms have been developed for this kind of radar, but the calculation burden is still heavy. So the image processing of SAR is normally performed “off-line”.</p><p>The Fast Factorized Back Projection (FFBP) algorithm is considered as a computationally efficient algorithm for image formation in SAR, and several applications have been implemented which try to make the process “on-line”.</p><p>CELL Broadband Engine is one of the newest multi-core-processor jointly developed by Sony, Toshiba and IBM. CELL is good at parallel computation and floating point numbers, which all fit the demands of SAR image formation.</p><p>This thesis is going to implement FFBP algorithm on CELL Broadband Engine, and compare the results with pre-projects. In this project, we try to make it possible to perform SAR image formation in real-time.</p>

Thesis (M.S.) -- Mississippi State University. Department of Computational Engineering. / Title from title screen. Includes bibliographical references.

En radiothérapie, la tomodensitométrie (CT) fournit l’information anatomique du patient utile au calcul de dose durant la planification de traitement. Afin de considérer la composition hétérogène des tissus, des techniques de calcul telles que la méthode Monte Carlo sont nécessaires pour calculer la dose de manière exacte. L’importation des images CT dans un tel calcul exige que chaque voxel exprimé en unité Hounsfield (HU) soit converti en une valeur physique telle que la densité électronique (ED). Cette conversion est habituellement effectuée à l’aide d’une courbe d’étalonnage HU-ED. Une anomalie ou artefact qui apparaît dans une image CT avant l’étalonnage est susceptible d’assigner un mauvais tissu à un voxel. Ces erreurs peuvent causer une perte cruciale de fiabilité du calcul de dose. Ce travail vise à attribuer une valeur exacte aux voxels d’images CT afin d’assurer la fiabilité des calculs de dose durant la planification de traitement en radiothérapie. Pour y parvenir, une étude est réalisée sur les artefacts qui sont reproduits par simulation Monte Carlo. Pour réduire le temps de calcul, les simulations sont parallélisées et transposées sur un superordinateur. Une étude de sensibilité des nombres HU en présence d’artefacts est ensuite réalisée par une analyse statistique des histogrammes. À l’origine de nombreux artefacts, le durcissement de faisceau est étudié davantage. Une revue sur l’état de l’art en matière de correction du durcissement de faisceau est présentée suivi d’une démonstration explicite d’une correction empirique. / Computed tomography (CT) is widely used in radiotherapy to acquire patient-specific data for an accurate dose calculation in radiotherapy treatment planning. To consider the composition of heterogeneous tissues, calculation techniques such as Monte Carlo method are needed to compute an exact dose distribution. To use CT images with dose calculation algorithms, all voxel values, expressed in Hounsfield unit (HU), must be converted into relevant physical parameters such as the electron density (ED). This conversion is typically accomplished by means of a HU-ED calibration curve. Any discrepancy (or artifact) that appears in the reconstructed CT image prior to calibration is susceptible to yield wrongly-assigned tissues. Such tissue misassignment may crucially decrease the reliability of dose calculation. The aim of this work is to assign exact physical values to CT image voxels to insure the reliability of dose calculation in radiotherapy treatment planning. To achieve this, origins of CT artifacts are first studied using Monte Carlo simulations. Such simulations require a lot of computational time and were parallelized to run efficiently on a supercomputer. An sensitivity study on HU uncertainties due to CT artifacts is then performed using statistical analysis of the image histograms. Beam hardening effect appears to be the origin of several artifacts and is specifically addressed. Finally, a review on the state of the art in beam hardening correction is presented and an empirical correction is exposed in detail.

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