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High-speed Multiplier Design Using Multi-Operand MultipliersNezhad, Mohammad Reza Reshadi, Navi, Kaivan 01 April 2012 (has links)
Multipliers are used in most arithmetic computing
systems such as 3D graphics, signal processing, and etc. It
is inherently a slow operation as a large number of partial
products are added to produce the result. There has been
much work done on designing multipliers [1]-[6]. In first
stage, Multiplication is implemented by accumulation of
partial products, each of which is conceptually produced
via multiplying the whole multi-digit multiplicand by a
weighted digit of multiplier. To compute partial products,
most of the approaches employ the Modified Booth
Encoding (MBE) approach [3]-[5], [7], for the first step
because of its ability to cut the number of partial products
rows in half. In next step the partial products are reduced
to a row of sums and a row of caries which is called
reduction stage. / Multiplication is one of the major bottlenecks in most digital
computing and signal processing systems, which depends on the
word size to be executed. This paper presents three deferent
designs for three-operand 4-bit multiplier for positive integer
multiplication, and compares them in regard to timing, dynamic
power, and area with classical method of multiplication
performed on today architects. The three-operand 4-bit
multipliers structure introduced, serves as a building block for
three-operand multipliers in general
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Design of parallel multipliers and dividers in quantum-dot cellular automataKim, Seong-Wan 21 June 2011 (has links)
Conventional CMOS (the current dominant technology for VLSI) implemented with ever smaller
transistors is expected to encounter serious problems in the near future with the need for difficult fabrication technologies. The most important problem is heat generation. The desire for device density, power dissipation and performance improvement necessitates new technologies that will provide innovative solutions to integration and computations. Nanotechnology, especially Quantum-dot Cellular Automata (QCA)
provides new possibilities for computing owing to its unique properties. Numerous nanoelectronic devices are being investigated and many experimental devices have been developed. Thus, high level circuit design is needed to keep pace with changing physical studies. The circuit design aspects of QCA have not been studied much because of its novelty. Arithmetic units, especially multipliers and dividers play an important role in the design of digital processors and application specific systems.
Therefore, designs for parallel multipliers and dividers are presented using this technology.
Optimal design of parallel multipliers for Quantum-Dot Cellular
Automata is explored in this dissertation. As a main basic element to build multipliers, adders are implemented and compared their performances with previous adders. And two different layout schemes that single layer and multi-layer wire crossings are compared and analyzed. This dissertation proposes three kinds of multipliers. Wallace and Dadda parallel multipliers, quasi-modular multipliers, and array multipliers are designed and simulated with several different operand sizes.
Also array multipliers that are well suited in QCA are constructed and formed by a regular lattice of identical functional units so that the structure is conformable to QCA technology without extra wire delay. All these designs are constructed using coplanar layouts and compared with other QCA multipliers. The delay, area and complexity are compared for several different operand sizes.
This research also studies divider designs for quantum-dot cellular automata. A digit recurrence restoring binary divider is a conventional design that serves as a baseline. By using controlled full subtractor cell units, a relatively simple and efficient implementation is realized. The Goldschmidt divider using the new architecture (data tag method) to control the various elements of the divider is compared for the performance. / text
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