The main goal of this thesis is to improve the efficiency of power consumption for single train and propose the effects of the voltage variation to AC/DC power flow. This thesis establishes a simplified mathematic model for motor drivers with the magnetic vector control laws. Furthermore, it designs the framework of the motor drives model with the power system blockset of the MATLAB/SIMULINK. The mass rapid transit(MRT) power system framework are also introduced in the thesis. Besides the power and propelment system model are developed. Due to the differences of the load pattern for the MRT system and the other customers, the analysis can be separated into static station load and dynamic load during the train operations. Static station load is constant and easy to measure. But dynamic load leads to some extent of variation depended on the MRT network characteristics and the headway of trains. The power consumption for dynamic load is about 60-70% of the whole MRT power consumption. The whole process of starting, acceleration, coasting and stopping are realistically concerned for the simulation of MRT operation. In this thesis, the DC system is composed of a 12 pulse rectifying transformer, a conductor rail, motor-driven induction drive control, VVVF inverter, and a 3-phase motor-driven induction electric power model. The performance for single train can be obtained very efficiently with the rate curves. To perform the MRT power system simulation, an AC/DC load flow analysis has been developed with Matlab. The power system model of an simulation for Taipei MRT system has been created, the AC/DC load flow analysis is executed to analyze the effects of traction substation, voltage fluctuation, and various load under the dynamic operation for multiple trains. The efficiency of proposed methodology to solve the optimal MRT operation is verified by comparing to the results of Train Performance Simulator (TPS), which has been used by Taipei MRT project. It is suggested that the proposed rigid modeling of propulsion driving system can enhance the accuracy of system simulation and provide the tool to achieve better planing of MRT operation.

Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFSbased NoC optimization techniques have been proposed. However, due to the resources required to validate architectural decisions through prototyping, few are implemented. As a result, designers are faced with a lack of insight into potential power savings or performance gains at early architecture stages. This thesis proposes a DVFS aware NoC simulator with support for per node power-frequency modeling to allow fine-tuning of such optimization techniques early on in the design cycle. The proposed simulator also provides a framework for benchmarking various candidate strategies to allow selective prototyping and optimization. As part of the research, DVFS extensions were built for an existing NoC performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each other. This thesis also serves as a technical manual for the simulator extensions. Important links for downloading and using the simulator are provided at the end of this document in Appendix C.