No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

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High-performance computing (HPC) variability management is an important topic in computer science. Research topics include experimental designs for efficient data collection, surrogate models for predicting the performance variability, and system configuration optimization. Due to the complex architecture of HPC systems, a comprehensive study of HPC variability needs large-scale datasets, and experimental design techniques are useful for improved data collection. Surrogate models are essential to understand the variability as a function of system parameters, which can be obtained by mathematical and statistical models. After predicting the variability, optimization tools are needed for future system designs. This dissertation focuses on HPC input/output (I/O) variability through three main chapters. After the general introduction in Chapter 1, Chapter 2 focuses on the prediction models for the scalar description of I/O variability. A comprehensive comparison study is conducted, and major surrogate models for computer experiments are investigated. In addition, a tool is developed for system configuration optimization based on the chosen surrogate model. Chapter 3 conducts a detailed study for the multimodal phenomena in I/O throughput distribution and proposes an uncertainty estimation method for the optimal number of runs for future experiments. Mixture models are used to identify the number of modes for throughput distributions at different configurations. This chapter also addresses the uncertainty in parameter estimation and derives a formula for sample size calculation. The developed method is then applied to HPC variability data. Chapter 4 focuses on the prediction of functional outcomes with both qualitative and quantitative factors. Instead of a scalar description of I/O variability, the distribution of I/O throughput provides a comprehensive description of I/O variability. We develop a modified Gaussian process for functional prediction and apply the developed method to the large-scale HPC I/O variability data. Chapter 5 contains some general conclusions and areas for future work. / Doctor of Philosophy / This dissertation focuses on three projects that are all related to statistical methods in performance variability management in high-performance computing (HPC). HPC systems are computer systems that create high performance by aggregating a large number of computing units. The performance of HPC is measured by the throughput of a benchmark called the IOZone Filesystem Benchmark. The performance variability is the variation among throughputs when the system configuration is fixed. Variability management involves studying the relationship between performance variability and the system configuration. In Chapter 2, we use several existing prediction models to predict the standard deviation of throughputs given different system configurations and compare the accuracy of predictions. We also conduct HPC system optimization using the chosen prediction model as the objective function. In Chapter 3, we use the mixture model to determine the number of modes in the distribution of throughput under different system configurations. In addition, we develop a model to determine the number of additional runs for future benchmark experiments. In Chapter 4, we develop a statistical model that can predict the throughout distributions given the system configurations. We also compare the prediction of summary statistics of the throughput distributions with existing prediction models.

Recent technologies have changed the way companies acquire and use computing resources. Companies have to adapt their capabilities, which combine business processes, skills, etc., to exploit the opportunities presented by these technologies whilst avoiding adverse effects. The latter part is, however, becoming increasingly difficult due to the uncertain long-term impact recent technologies have. This thesis argues that companies are required to adapt their capabilities in a way that increases the company's resilience so that they are robust yet flexible enough to succeed under uncertain conditions. By focusing on cloud computing as one recent technology, this thesis first identifies the underlying processes of adapting capabilities to cloud computing by investigating how software vendors migrated their products into the cloud. The results allow the definition of viewpoints that influence the adaptation of capabilities to cloud computing. Furthermore, the Functional Resonance Analysis Method (FRAM) is applied to one software vendor after the migration of their product into the cloud. FRAM enables the analysis of ‘performance variabilities' that need to be dampened to increase the resilience of systems. The results show that FRAM appropriately informs steps to increase and measure resilience when migrating products into the cloud. The final part develops cFRAM which extends FRAM through the viewpoints to enable the analysis of capabilities within FRAM. The goal of cFRAM is to enable companies to (1) identify existing capabilities, (2) investigate the impact of cloud computing on them, and (3) inform steps to adapt them to cloud computing whilst dampening performance variabilities. The results of the cFRAM evaluation study are unequivocal and show cFRAM is a novel method that achieves its goal of enabling companies to adapt their capabilities to cloud computing in a way that increases the company's resilience. cFRAM can be easily adapted to other technologies like smartphones by changing the viewpoints.

Background: Low morale is classified as a latent condition for performance variability in safety-critical environments. Morale management may assist in the control of performance variability as part of a systems approach to safety. A context-specific model for measuring and managing morale with reference to followership in a safety-critical air traffic control (ATC) environment could not be found. Purpose/Aim: The purpose of this study was to develop a model that enables the measurement and management of air traffic controller (ATCO) team morale. Research Design: An exploratory sequential mixed method design was adopted. A census approach to sampling was used to conduct 21 focus group sessions as the qualitative phase, providing the definition and drivers of morale. The Measure of Morale and its Drivers (MoMaD) survey instrument was created from qualitative data, then administered to 256 ATCOs in the quantitative phase. Statistical methods included exploratory factor analysis, correlation and regression analysis to construct the final MoMaD model. Results: A context-specific definition of morale is provided and communication management, team cohesion, leadership interaction, staff incentive, staffing level, workplace health and safety and mutual trust were found to be the drivers of morale in a safety-critical ATC environment. A single-item measure of perceived morale reflected the state of context-specific ATCO team morale more accurately than an existing generalisable multi-item measure. Conclusion: This study contributes to the body of knowledge by integrating applicable aspects of morale, followership, performance variability and organisational culture and climate in safety-critical ATC environments into a new theoretical framework. The MoMaD instrument is presented as a context-specific model for measuring and managing ATCO team morale in an ATC environment. Recommendations: Future research opportunities include the possible influence of morale as a predictor of morale in safety-critical environments and the development of a context-specific multi-item measure of morale for integration into the MoMaD model. / Business Management / D. B. L.

FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico / O escalonamento de recursos à um processo chave para a plataforma de ComputaÃÃo em Nuvem, que geralmente utiliza mÃquinas virtuais (MVs) como unidades de escalonamento. O uso de tÃcnicas de virtualizaÃÃo fornece grande flexibilidade com a habilidade de instanciar vÃrias MVs em uma mesma mÃquina fÃsica (MF), modificar a capacidade das MVs e migrÃ-las entre as MFs. As tÃcnicas de consolidaÃÃo e alocaÃÃo dinÃmica de MVs tÃm tratado o impacto da sua utilizaÃÃo como uma medida independente de localizaÃÃo. à geralmente aceito que o desempenho de uma MV serà o mesmo, independentemente da MF em que ela à alocada. Esta à uma suposiÃÃo razoÃvel para um ambiente homogÃneo, onde as MFs sÃo idÃnticas e as MVs estÃo executando o mesmo sistema operacional e aplicativos. No entanto, em um ambiente de ComputaÃÃo em Nuvem, espera-se compartilhar um conjunto composto por recursos heterogÃneos, onde as MFs podem variar em termos de capacidades de seus recursos e afinidades de dados. O objetivo principal deste trabalho à apresentar uma arquitetura que possibilite a padronizaÃÃo da representaÃÃo do poder de processamento das MFs e MVs, em funÃÃo de Unidades de Processamento (UPs), apoiando-se na limitaÃÃo do uso da CPU para prover isolamento de desempenho e manter a capacidade de processamento das MVs independente da MF subjacente. Este trabalho busca suprir a necessidade de uma soluÃÃo que considere a heterogeneidade das MFs presentes na infraestrutura da Nuvem e apresenta polÃticas de escalonamento baseadas na utilizaÃÃo das UPs. A arquitetura proposta, chamada FairCPU, foi implementada para trabalhar com os hipervisores KVM e Xen, e foi incorporada a uma nuvem privada, construÃda com o middleware OpenNebula, onde diversos experimentos foram realizados para avaliar a soluÃÃo proposta. Os resultados comprovam a eficiÃncia da arquitetura FairCPU em utilizar as UPs para reduzir a variabilidade no desempenho das MVs, bem como para prover uma nova maneira de representar e gerenciar o poder de processamento das MVs e MFs da infraestrutura. / Resource scheduling is a key process for cloud computing platform, which generally uses virtual machines (VMs) as scheduling units. The use of virtualization techniques provides great flexibility with the ability to instantiate multiple VMs on one physical machine (PM), migrate them between the PMs and dynamically scale VMâs resources. The techniques of consolidation and dynamic allocation of VMs have addressed the impact of its use as an independent measure of location. It is generally accepted that the performance of a VM will be the same regardless of which PM it is allocated. This assumption is reasonable for a homogeneous environment where the PMs are identical and the VMs are running the same operating system and applications. Nevertheless, in a cloud computing environment, we expect that a set of heterogeneous resources will be shared, where PMs will face changes both in terms of their resource capacities and as also in data affinities. The main objective of this work is to propose an architecture to standardize the representation of the processing power by using processing units (PUs). Adding to that, the limitation of CPU usage is used to provide performance isolation and maintain the VMâs processing power at the same level regardless the underlying PM. The proposed solution considers the PMs heterogeneity present in the cloud infrastructure and provides scheduling policies based on PUs. The proposed architecture is called FairCPU and was implemented to work with KVM and Xen hypervisors. As study case, it was incorporated into a private cloud, built with the middleware OpenNebula, where several experiments were conducted. The results prove the efficiency of FairCPU architecture to use PUs to reduce VMsâ performance variability, as well as to provide a new way to represent and manage the processing power of the infrastructureâs physical and virtual machines.