The semiconductor industry has seen a paradigm shift from Application Specific Integrated Circuits to Multiprocessor System on Chip systems over the last decade, primarily due to the miniaturization of the transistor. However, billion of transistors available on a single chip need to be used efficiently to provide more functionalities in portable devices, yet minimize power and chip area, which increases the design complexity of multiprocessor systems. Tighter time to market deadlines further pressurizes the designer, requiring a comprehensive automation of the design process of such complex multiprocessor systems. This thesis presents a design automation methodology for the design of Multiprocessor System on Chip (MPSoC) systems for multimedia applications. This thesis introduces a heterogeneous multiprocessor system where processing elements are connected in a pipelined fashion. A multimedia application is executed very efficiently on a pipelined system due to the stream oriented data flow nature of such applications. Application Specific Instruction set Processors (ASIPs) are used as the elementary processing elements in the multiprocessor system as they can be customized according to the application tasks assigned to them. The problem of selecting a processor configuration for each of the ASIPs in the pipelined system is formalized. We present three different techniques to select processor configurations by exploring the design space of an ASIP based pipelined system, and integrating them into a flexible and designer driven design flow for efficient exploration of large design spaces in order of 10^16 design points. The first two techniques are based on Integer Linear Programming (ILP), named Exact ILP formulation (EIF) and Reduced ILP formulation (RIF), while the third technique is based on a novel heuristic. We also developed a design space pruning algorithm that can enable the use of EIF and RIF to obtain optimal or near optimal design points from large design spaces. For four multimedia applications, we show that RIF and the heuristic can explore the design space and reveal the Pareto front in several hours, while EIF took several days to obtain the Pareto front. The quick availability of the Pareto front of a design space will help the designer to make early changes in the design. Furthermore, it is shown that, on average, the error incurred by RIF and the heuristic is within 1.25% and 2.25% of the optimal design points obtained via EIF for all the four multimedia applications. In the worst case, RIF introduced an error of 17.08% while the heuristic had an error of 11.39%.