This work explores the application of various power amplifier design techniques for mobile communications. Several circuit configurations including class A amplifier, Doherty amplifier and power combining amplifier have been developed, which are to improve the performance of power amplifiers in terms of power added efficiency transmission power and bandwidth. In chapter 2, the cascode PA adopting tuning capacitor structure is proposed and implemented to enhance the efficiency. In chapter 3, a novel Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is introduced. Moreover, the second harmonic cancellation function of balun combining PA is analysed and verified with experimental results in chapter 4. The fully integrated cascode class A amplifier adopts RC negative feedback, which is to enhance bandwidth and input/output matching. The integrated choke inductor compensating the parasitic capacitor of transistors has very low quality factor, which decreases the efficiency of the power amplifier. To reduce the inductance value of the choke inductor, a tuning capacitor is connected in parallel with the choke inductor. As a result, the inductor resistance is reduced as well, which diminishes the power consumption induced by the resistance of the choke inductor. This proposed PA configuration is validated by simulation results with the PAE improved by 3 % at the 1 dB compression point compared to the topology without tuning capacitor. The experimental results demonstrate a PA which delivers an output power of 21.3 dBm with PAE of 21 % at the 1 dB compression point. The Doherty amplifier with 2-way Wilkinson power splitter is integrated in a 0.9 mm×1.8 mm chip. The main and peak amplifier adopt cascode configuration to improve the stability of the Doherty amplifier. To minimize the chip size, the quarter wave transmission line in the topology is replaced by π-type lumped element equivalent network. To increase the operating bandwidth, the Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is proposed. The topology consists of 3-stage RC polyphase filter, drive amplifiers, main amplifier, peak amplifier, and impedance inverter. By employing the polyphase filter, the quarter-wave transmission line at the input of the peak amplifier for compensating the phase shift of the impedance inverter is eliminated. According to the analysis of the polyphase filter prototype, the 3-stage polyphase filter is selected, and the component parameters are determined. The main amplifier and peak amplifier are using differential cascode configuration. The drive amplifier is to increase the power gain and provide proper impedance matching for the Doherty amplifier. The results demonstrate an outstanding broadband Doherty amplifier with a bandwidth of 1.8 GHz. The chip temperature rises dramatically due to the high power consumption of power amplifier. Consequently, the collector currents of the SiGe transistors are varying with the changing temperature, which deteriorates the PA performance. In the improved 3-stage PPF Doherty design, the bias voltages of the transistors in the first version 3-stage PPF Doherty amplifier are replaced by reference currents feeding through bias circuits. With current sources providing bias current to the transistors, the performance of the improved Doherty amplifier is enhanced. The power combining PAs are constructed on FR-4 PCB boards using discrete components. The single ended power amplifier in the power combining PA is built with high linearity HEMT transistor. The balun combining PA has an advantage of second harmonic cancellation, which is validated by both analysis and measurements. Moreover, power combining PAs with 2-way transmission line and lumped element Wilkinson power divider are designed. The transmission lines in these designs are analyzed using EM simulation tool and verified with testing structures on PCB boards.