Spelling suggestions: "subject:"power grid aanalysis"" "subject:"power grid 2analysis""
1 |
Power Grid Analysis In VLSI DesignsShah, Kalpesh 03 1900 (has links)
Power has become an important design closure parameter in today’s ultra low submicron
digital designs. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, system, board and package thermal analysis, power grid design and signal integrity analysis to minimizing power itself. This work focuses on challenges arising due to increase in power to power grid design and analysis.
Challenges arising due to lower geometries and higher power are very well researched topics and there is still lot of scope to continue work. Traditionally, designs go through average IR drop analysis. Average IR drop analysis is highly dependent on current dissipation estimation. This work proposes a vector less probabilistic toggle estimation which is extension of one of the approaches proposed in literature. We have further used toggles computed using this approach to estimate power of ISCAS89 benchmark circuits. This provides insight into quality of toggles being generated. Power Estimation work is further extended to comprehend with various state of the art methodologies available i.e. spice based power estimation, logic simulation based power estimation, commercially available tool comparisons etc. We finally arrived at optimum flow recommendation which can be used as per design need and schedule.
Today’s design complexity – high frequencies, high logic densities and multiple level clock and power gating - has forced design community to look beyond average IR drop. High rate of switching activities induce power supply fluctuations to cells in design which is known as instantaneous IR drop. However, there is no good analysis methodology in place to analyze this phenomenon. Ad hoc decoupling planning and on chip intrinsic decoupling capacitance helps to contain this noise but there is no guarantee. This work also applies average toggle computation approach to compute instantaneous IR drop analysis for designs. Instantaneous IR drop is also known as dynamic IR drop or power supply noise. We are proposing cell characterization methodology for standard cells. This data is used to build power grid model of the design. Finally, the power network is solved to compute instantaneous IR drop.
Leakage Power Minimization has forced design teams to do complex power gating – multilevel MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid in terms of ON/OFF sequencing and noise injection due to it. This work explains the state of art here and highlights some of the issues and trade offs using MTCMOS logic. It further suggests a simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms of peak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gate optimization. Early leakage optimization overhead can be computed using this approach.
|
2 |
Modeling and Analysis of Large-Scale On-Chip InterconnectsFeng, Zhuo 2009 December 1900 (has links)
As IC technologies scale to the nanometer regime, efficient and accurate modeling
and analysis of VLSI systems with billions of transistors and interconnects becomes
increasingly critical and difficult. VLSI systems impacted by the increasingly high
dimensional process-voltage-temperature (PVT) variations demand much more modeling
and analysis efforts than ever before, while the analysis of large scale on-chip
interconnects that requires solving tens of millions of unknowns imposes great challenges
in computer aided design areas. This dissertation presents new methodologies
for addressing the above two important challenging issues for large scale on-chip interconnect
modeling and analysis:
In the past, the standard statistical circuit modeling techniques usually employ
principal component analysis (PCA) and its variants to reduce the parameter
dimensionality. Although widely adopted, these techniques can be very
limited since parameter dimension reduction is achieved by merely considering
the statistical distributions of the controlling parameters but neglecting
the important correspondence between these parameters and the circuit performances
(responses) under modeling. This dissertation presents a variety of
performance-oriented parameter dimension reduction methods that can lead to
more than one order of magnitude parameter reduction for a variety of VLSI
circuit modeling and analysis problems.
The sheer size of present day power/ground distribution networks makes their
analysis and verification tasks extremely runtime and memory inefficient, and
at the same time, limits the extent to which these networks can be optimized.
Given today?s commodity graphics processing units (GPUs) that can deliver
more than 500 GFlops (Flops: floating point operations per second). computing
power and 100GB/s memory bandwidth, which are more than 10X greater
than offered by modern day general-purpose quad-core microprocessors, it is
very desirable to convert the impressive GPU computing power to usable design
automation tools for VLSI verification. In this dissertation, for the first time, we
show how to exploit recent massively parallel single-instruction multiple-thread
(SIMT) based graphics processing unit (GPU) platforms to tackle power grid
analysis with very promising performance. Our GPU based network analyzer
is capable of solving tens of millions of power grid nodes in just a few seconds.
Additionally, with the above GPU based simulation framework, more challenging
three-dimensional full-chip thermal analysis can be solved in a much more
efficient way than ever before.
|
Page generated in 0.0502 seconds