Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms which reduces power consumption of the receiver. The work in the thesis ranges from designing low power architecture of the receiver to experimentally verifying the functioning of the receiver. Concepts proposed in the thesis are: Low power adaptive architecture :-A baseband digital receiver design is proposed which changes its sampling frequency and bit-width based on interference detection and SNR estimation. The approach is based on Look-up-table (LUT) in the digital section of the receiver. Interference detector and SNR estimator has been proposed which suits this approach. Settings of different sections of digital receiver changes as sampling frequency and bit-width varies. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. It is shown that the power consumption by the digital baseband can be reduced by 85% (7 times) when there is no interference and SNR is high. Thus the proposed design meets our requirement of low power hardware. The design is coded in Verilog HDL and power and area estimation is done using Synopsys tools. Faster Simulation Methodologies :-Usually physical layer simulations are done on baseband equivalent model of the signal in the receiver chain. Simulating Physical layer algorithms on bandpass signals for BER evaluation is very time consuming. We need to do the bandpass simulations to capture the effect of quantization on bandpass signal in the receiver. We have developed a variance measuring simulation methodology for faster simulation which reduces simulation time by a factor of 10. Low power, Low area, Non-coherent, Non-data-aided joint tracking and acquisition algorithm :-Correlation is a very popular function used particularly in synchronization algorithms in the receivers. But correlation requires usage of multipliers. Multipliers are area and power consuming blocks. A very low power and low area joint tracking and acquisition algorithm is developed. The algorithm does not use any multiplier to synchronize. Even it avoids squaring and adding the signals to achieve non-coherency. Beside the algorithm is non-data-aided as well and does not require ROM to store the sequence. The Algorithm saves area/power of existing similar algorithms by 90%. Experimental setup for performance evaluation of the receiver :-The developed baseband architecture and algorithms are experimentally verified on a wireless test setup. Wireless test setup consists of FPGA board, VSGs, Oscilloscopes, Spectrum analyzer and a discrete component RF board. Packet error and packet loss measurement is done by varying channel conditions. Many practical and interesting issues dealing with wireless test setup infrastructure were encountered and resolved.