The explosive growth of the wireless market has increased the demand for low-cost, highly-integrated CMOS wireless transceivers. However, the implementation of CMOS RF power amplifiers remains a formidable challenge. The objective of this research is to demonstrate the feasibility of CMOS RF power amplifiers by compensating for the RF performance disadvantages of CMOS technology. This dissertation proposes a parallel-combining transformer (PCT) as an impedance-matching and output-combining network. The results of a comprehensive analysis show that the PCT is a suitable solution for watt-level output power generation in cellular applications. To achieve high output power and high efficiency, the work presented here entailed the design of a class-E switching power amplifier in a 0.18-μm CMOS technology for GSM applications and, with the suggested power amplifier design technique, successfully demonstrated a fully-integrated RF front-end consisting of a power amplifier and an antenna switch. This dissertation also proposed an efficiency enhancement technique at power back-off. In an effort to save current in the power back-off while satisfying the EVM requirements, a class-AB linear power amplifier was implemented in a 0.18-μm CMOS technology for WLAN and WiMAX applications using a PCT as well as an operation class shift between class-A and class-B. Thus, the research in this dissertation provides low-cost CMOS RF power amplifier solutions for commercial products used in mobile wireless communications.