Thesis (M.S. in Applied Physics)--Naval Postgraduate School, June 2009. / Thesis Advisor(s): Weatherford, Todd R. "June 2009." Description based on title screen as viewed on July 14, 2009. Author(s) subject terms: gallium nitride, HEMT, high electron mobility transistor, Silvaco, ATLAS, modeling, transient, self-heating, pulse. Includes bibliographical references (p. 73-74). Also available in print.

No description available.

M.Ing. (Electrical & Electronic Engineering) / The technology of the use of electronic devices as power switches is still being developed. Because of the increasing demand for low mass and cost, the switching frequency must be as high as possible. The limiting factor for the frequency is the energy loss which is dissipated in the semiconductor crystal during each switching-transient. If tllis switching loss can be reduced, a higher frequency can be obtained. The switching loss is due to the non-instantaneous switching process of the semiconductor device. For the reduction of this switching loss, the device must be switched as fast as possible via its control-electrode. Further improvement can be obtained through the use of snubber networks. This thesis considers the bipolar high-voltage transistor as a power switch. The unfavourable switching loci of the transistor- switch is discussed in chapter 1. In chapter 2 the basedrive during transistor turn-off is investigated, in order to reduce the turn-off time. The following chapters de;al with the use of snubber circuits, which relieve the transistor during turn-on and turn-off. The advantages, as well as the disadvantages and limitations of snubbers are discussed. After the linear turn-off and turn-on snubbers have been treated, the non-linear turn-on snubber, which uses a saturable inductor, will be considered from an experimental point of view. The results show that this snubber is very effective in relieving the transistor during turn-on. In chapter 7 the non-linear turn-off snubber is treated on an experimental as well as on a mathematical bas e . Cri teria, which must be satisfied for realisation of a practical nonlinear capacitor, is also laid down. Because of the fact that a first order snubber is always loading the transistor during the complimentary switchin,]-transient, chapter 8 deals with a second order snubber, which consists of both a capacitor and an inductor. Experimentally it was found that the turn-on time is reduced with the use of a turn-on snubber, while the turn-off time is increased with the use of a turn-off snubber. In chapter 9 the physical behaviour of the switching processes is investigated, after which the influences of the snubbers on the switching times is explained qualitatively...

When electronic components are to be used in systems destined for operation in the extraterrestrial environment, one must be concerned about the effects of the naturally occurring radiation in outer space. For example, power metal-oxide-semiconductor-field-effect transistors (MOSFETs) and power bipolar junction transistors (BJTs) are susceptible to a phenomenon called single-event burnout (SEB) which may result from bombardment by heavy ions originating from the nuclear reactions within the sun and other stars. SEB is a catastrophic failure mechanism initiated by the passage of a heavy ion through sensitive regions of the power MOSFET or power BJT. The main thrust of this dissertation is an analytical model describing the device-related aspects of the SEB mechanism. Physical device parameters such as doping concentrations, dimensions of various regions, and operating bias are related to SEB by the model. It is shown that the model predicts a decrease in the SEB susceptibility with a decrease in the internal base resistance (in the power BJT or parasitic BJT in the power MOSFET structure), a decrease in the operating bias, or an increase in the ambient device temperature. These findings are then qualitatively verified with experimental data.

<p>To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power.Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components.In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly non-uniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed.</p>

To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power.Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components.In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly non-uniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

M.Ing. (Electrical And Electronic Engineering) / DC to AC converters are used daily in industry, shipping and aviation as power .. supplies, standby power supplies or uninterrupted power supplies. Power levels vary from a few watts to several megawatts. This thesis investigates a composite converter with a high frequency link as such a DC to AC converter. There are two basic building blocks, the primary inverter as a push-pull inverter and the secondary converter as a cyclo-converter. A existing 2.5kVA system with bipolar transistors in the primary inverter and asymmetrical thyristors in the secondary converter is investigated. In the primary inverter, regenerative snubbers are used to minimise switching losses. A second 2.5kVA system with mosfets in the primary inverter and IGBT's in the secondary is developed. Switching losses in the primary inverter are minimised by including a resonant circuit concisting of a non-linear inductor and linear capacitor. This resonant circuit in the primary inverter, was originally simmulated by a PSPICE simmulation program, after which it was build up experimentally. The simmulated results and experimental results coincided, and development of the secondary converter started. The switches in the secondary had to comply to two conditions viz, low conducting lossses and the ability to switch at switching frequencies higher than 20kHz. IGBT's were consequently chosen and were implemented with the necessary gate drive circuits. With the higher switching frequency of 25kHz to the 5kHz of the first system, the ripple on the load current was significantly reduced. Furthermore, the construction of the composite converter with the gate drive switches was easy and compact, and the total cost of developing such a converter were reduced.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1980. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Charles Edward Harm. / M.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Thomas Raymond Zaloum. / M.S.