Enrollment in Massive Open Online Courses (MOOCs) and other open distance education is increasing and this requires large numbers of problems for students to learn from. Additionally, students learning programming benefit from practicing their skills on programming problems. Researchers have turned to automatically generating problems for this reason, although rarely within the domain of computer science. Those that are within that domain are limited in the variety of tasks they can generate. This means that students must come up with their own practice or rely on educators to create them manually, which is a demanding task. This research demonstrates a tool that can generate a suite of randomized programming problems to challenge students from instructor-defined templates. The tool will also come with an evaluation program to provide relevant statistics that instructors can use to evaluate the variety and complexity of problems in their suite.

Visibility culling is a means of accelerating the graphical rendering of geometric models. Invisible objects are efficiently culled to prevent their submission to the standard graphics pipeline. It is advantageous to preprocess scenes in order to determine invisible objects from all possible camera views. This information is typically saved to disk and may then be reused until the model geometry changes. Such preprocessing algorithms are therefore used for scenes that are primarily static. Currently, the standard approach to visibility preprocessing algorithms is to use a form of approximate solution, known as conservative culling. Such algorithms over-estimate the set of visible polygons. This compromise has been considered necessary in order to perform visibility preprocessing quickly. These algorithms attempt to satisfy the goals of both rapid preprocessing and rapid run-time rendering. We observe, however, that there is a need for algorithms with superior performance in preprocessing, as well as for algorithms that are more accurate. For most applications these features are not required simultaneously. In this thesis we present two novel visibility preprocessing algorithms, each of which is strongly biased toward one of these requirements. The first algorithm has the advantage of performance. It executes quickly by exploiting graphics hardware. The algorithm also has the features of output sensitivity (to what is visible), and a logarithmic dependency in the size of the camera space partition. These advantages come at the cost of image error. We present a heuristic guided adaptive sampling methodology that minimises this error. We further show how this algorithm may be parallelised and also present a natural extension of the algorithm to five dimensions for accelerating generalised ray shooting. The second algorithm has the advantage of accuracy. No over-estimation is performed, nor are any sacrifices made in terms of image quality. The cost is primarily that of time. Despite the relatively long computation, the algorithm is still tractable and on average scales slightly superlinearly with the input size. This algorithm also has the advantage of output sensitivity. This is the first known tractable exact solution to the general 3D from-region visibility problem. In order to solve the exact from-region visibility problem, we had to first solve a more general form of the standard stabbing problem. An efficient solution to this problem is presented independently.

This dissertation addresses the issues of high power consumption and verification associated with a novel hardware design methodology based on high-level synthesis using action-oriented specifications. High-level synthesis of hardware designs is the process of automatically converting high-level behavioral specifications of designs into their corresponding RTL (Register Transfer Level) descriptions. From a designer's perspective, writing high-level specifications of a design alleviates the burden of handling various scheduling and concurrency issues, which can be automatically handled by the high-level synthesis tool. In the recent past, EDA (Electronic Design Automation) industry has seen efforts by various vendors to make such synthesis process practical for generating efficient hardware designs. In most of these cases, the inputs to high-level synthesis tools are the control data-flow graphs (CDFGs) or hierarchical variants of those. These models sequentialize parts of the computation in the form of computation threads. In contrast, in the last couple of years, advances have been made in an alternative high-level hardware design methodology where the specifications are action-oriented rather than the composition of sequential threads. In this paradigm, a hardware design is described in terms of atomic actions and then synthesized into the RTL code. Action-oriented synthesis process inherently targets the reduction of area and latency of a hardware design. However, two important issues that have not been addressed adequately are (1) power optimizations during such synthesis and (2) verification of action-oriented specifications and synthesized power-minimized implementations of the designs. With the proliferation of power-hungry portable devices, ever shrinking geometries and increasing clock frequencies, power consumption of hardware designs has become a critical metric (besides area and latency) that should be taken into consideration while evaluating the viability and success of a synthesis process. In this work, we analyze the complexity of low-power problems associated with the action-oriented specification models, and propose algorithms and techniques for power optimization during the action-oriented synthesis process. Furthermore, verification of hardware designs generated from such models is required in order to verify the changes caused in their structures or behaviors as part of any used power minimization techniques. Verification of high-level action-oriented models is also important for ensuring the correctness of the designs early in the design cycle. In this work, we also propose various formal verification techniques that can be used for verifying desired correctness properties as well as behaviors of power-minimized action-oriented designs at high-level. / Ph. D.