Thesis--PlanB (M.S.)--University of Wisconsin--Stout, 2002. / Includes bibliographical references.

An integrated circuit processing schedule is presented that enables fabrication of both high speed I²L gates and high voltage linear type transistors on the same silicon starting substrate material. This process design circumvents conflicting processing requirements normally encountered in considering an I²L/Linear compatible structure by providing two separate epitaxial thicknesses for the I²L and linear section of the chip. The electrical characteristics of the I²L cells and the linear transistors are presented to illustrate their dependence on the doping conditions and are shown to be in contrast to each other. As a consequence of the separate epitaxial thicknesses, independence of the processing constraints is achieved. Experimental results of linear transistors and I²L devices fabricated using this processing schedule are presented and compared to calculated and computer simulations. Modifications to the basic process design is shown possible and enhanced performance of I²L devices results.

No description available.

No description available.

Thesis (M.S.)--Ohio University, August, 1992. / Title from PDF t.p.

Akademisk avhandling--Handelshögskolan i Göteborg. / Extra t.p. with thesis statement inserted. Bibliography: p. 46-47.

Thesis (Ph. D.)--University of Hong Kong, 1992.

Thesis (Ph. D.)--University of Hong Kong, 1998. / Includes bibliographical references.

Thesis (M.S.)--University of Wisconsin--Madison, 1966. / eContent provider-neutral record in process. Description based on print version record. Bibliography: l. 93-94.

No description available.