Localized heating leads to generation of thermal Hotspots that affect performance and reliability of an Integrated Circuit(IC). Functional workloads determine the locations and temperature of hotspots on a die. Programs are classified into phases based on program execution profile. During a phase, spatial power dissipation pattern of an application remains unchanged. In this thesis, we present a systematic approach for developing a synthetic workload from a functional workload to create worst case temperature of a target hotspot in 2D and 3D IC. These synthetic workload are designed to create thermal stress patterns, which would help in characterizing the thermal characteristics of micro architecture to worst case temperature transient which is an important problem in Industry. Our approach is based on the observation that, worst case temperature at a particular location in 2 D IC is determined not only by the current activity in that region, but also by the past activities in the surrounding regions. Therefore, if the surrounding areas were “pre-heated” with a different workload, then the target region may become hotter due to slower rate of lateral heat dissipation Similarly in case of 3D IC, the workload applied to each of the dies in 3D IC keeps on changing continuously, thus the hotspot could be found in any of the stacked layers. Thus the creation of localized hotspot at a particular location in a stacked 3D IC layer depends not only on the present activity at that location but also on the previous activity in the surrounding region and also on the activity of layers below it. Accordingly, (i) we develop a wavelet-based canonical spatio-temporal heat dissipation model for program traces, and use (ii) a novel Integer Linear Programming (ILP) formulation to rearrange program phases to generate target worst case hotspot temperature in 2D and 3D IC. We apply this formulation to target another well-known problem of (iii) maximizing temperature between a pair of co-ordinates in an IC. Experimental results show that by taking the spatio-temporal effect into account and with dynamic phase change behavior, we could raise temperature of a hotspot higher than what is possible otherwise. ICs are often tested at worst-case system operating conditions to assure that, all ICs shipped will function properly in the end system. Thus hotspot temperature maximization is an important in design verification and testing.

Estimating program worst case execution time (WCET) is an important problem in the domain of real-time systems and embedded systems that are deadline-centric. If WCET of a program is found to exceed the deadline, it is either recoded or the target architecture is modified to meet the deadline. Predominantly, there exist three broad approaches to estimate WCET- static WCET analysis, hybrid measurement based analysis and statistical WCET analysis. Though measurement based analyzers benefit from knowledge of run-time behavior, amount of instrumentation remains a concern. This thesis proposes a CPI-centric WCET analyzer that estimates WCET as a product of worst case instruction count (IC) estimated using static analysis and worst case cycles per instruction (CPI) computed using a function of measured CPI. In many programs, it is observed that IC and CPI values are correlated. Five different kinds of correlation are found. This correlation enables us to optimize WCET from the product of worst case IC and worst case CPI to a product of worst case IC and corresponding CPI. A prime advantage of viewing time in terms of CPI, enables us to make use of program phase behavior. In many programs, CPI varies in phases during execution. Within each phase, the variation is homogeneous and lies within a few percent of the mean. Coefficient of variation of CPI across phases is much greater than within a phase. Using this observation, we estimate program WCET in terms of its phases. Due to the nature of variation of CPI within a phase in such programs, we can use a simple probabilistic inequality- Chebyshev inequality, to compute bounds of CPI within a desired probability. In some programs that execute many paths depending on if-conditions, CPI variation is observed to be high. The thesis proposes a PC signature that is a low cost way of profiling path information which is used to isolate points of high CPI variation and divides a phase into smaller sub-phases of lower CPI variation. Chebyshev inequality is applied to sub-phases resulting in much tighter bounds. Provision to divide a phase into smaller sub-phases based on allowable variance of CPI within a sub-phase also exists. The proposed technique is implemented on simulators and on a native platform. Other advantages of phases in the context of timing analysis are also presented that include parallelized WCET analysis and estimation of remaining worst case execution time for a particular program run.