The thesis deals with issues of random numbers, their generating and use in cryptography. Introduction of work is aimed to resolution of random number generators and pseudo--random number generators. There is also included often used dividing generators on software and hardware. We mention advantages and disadvantages of each type and area of their use. Then we describe examples of random and pseudorandom numbers, mainly hardware based on physical phenomenon such as the decay of radioactive material or use atmospheric noise. The following part is devoted to suggestion own random number generator and a description of its functionality. In the second half of the work we devote to the field of cryptography. We know basic types of cryptographic systems, namely symmetric and asymmetric cryptosystems. We introduce a typical representant the various type and their properties. At the end of the work we again return to our random number generator and verify the randomness generated numbers and obtained cryptograms.

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Low Density Parity Check (LDPC) codes are the parity check codes of long block length, whose parity check matrices have relatively few non-zero entries. To improve the performance at relatively short block lengths, LDPC codes are constructed by either pseudo-random or quasi-cyclic methods instead of random construction methods. In this thesis, pseudo-random code construction methods, the effects of closed loops and the graph connectivity on the performance of pseudo-random LDPC codes are investigated. Moreover, quasi-cyclic LDPC codes, which have encoding and storage advantages over pseudo-random LDPC codes, their construction methods and performances are reviewed. Finally, performance comparison between pseudo-random and quasi-cyclic LDPC codes is given for both regular and irregular cases.

Third generation mobile communication systems promise a greater data rate and new services to the mobile subscribers. 3G systems support up to 2 Mbps of data rate to a fixed subscriber and 144 Kbps of data rate to a fully mobile subscriber. Code Division Multiple Access (CDMA) is the air interface access scheme widely used in all the 3G communication systems. This access scheme has many inherent advantages m terms of noise immunity, security, coherent combining of multi path signals etc. But all these advantages come at the expense of higher complexity of the receivers. The receivers form the major portion of the processing involved in a base station. The heart of any CDMA receiver is the RAKE. The RAKE receiver separates the different multi-paths received by the antenna by using the properties of the Pseudo Random sequences. The phase and strength of each of these path signals is measured and are used by the coherent combiner, which de-rotates all the signals to a single reference and coherently combines them In general the Base station receivers make use of the top three multi-path signals ranked in terms of their signal energy Hence four RAKE fingers, each catering to single multi-path are needed for receiving a single code channel (3 for coherent combining and one for scanning). One such channel receiver requires a processing power of 860 MIPS (Mega Instructions Per Second). Some of the CDMA standards support up to 90 code channels at the same time. This means that the total processing power required at the base station is about 80 GIPS. This much of processing power will require large number of high end DSPs, which will be a very costly solution. In the current base station architectures these blocks are implemented using ASICs, which are specific to a particular standard and also the algorithms used for the different operations are fixed at the design time itself. This solution is not flexible and is not amenable for SDR (Software defined Radio) architectures for the Base stations. This thesis proposes a Co-Processor solution, which can be attached to a generic DSP or any other processor. The processor can control the Co-Processor by programming its parameter registers using memory mapped register accesses. This co-processor implements only those blocks, which are compute intensive. This co-processor performs all chip-rate processing functions involved m a RAKE receiver. All the symbol-rate functions are implemented through software in the processor. This provides more choices m selecting the algorithms for timing recovery and scanning. The algorithms can be changed through software even after the base station is installed in the field. All the inputs and outputs of the Co-Processor are passed through dual port RAMs with independent read and write clocks. This allows the Co-Processor and the processor to be running on two independent clocks. This memory scheme also increases the throughput as the reads and writes to these memories can happen simultaneously. This thesis introduces a concept of incorporating programmable PN/Gold code generators as part of the Co-Processor, which significantly reduces the amount of memory required to store the Scrambling and Spreading codes. The polynomial lengths as well as the polynomials of the code generator are programmable. The input signal memory has a bus width equal to 4 times the bus width of the IQ signal bus width (4 * 24 = 96 bits) towards the Co-Processor to meet the huge data bandwidth requirement. This memory is arranged as word interleaved memory banks. This can supply one word per memory bank on each clock cycle as long as the accessed words fall in different memory banks. The number of banks is chosen as more than twice that of the number of Correlators/ Rake fingers. This gives more flexibility in choosing the address offsets to different Correlator inputs. This flexibility allows one to use different timing recovery schemes since the number of allowable address offsets for different Correlators is more. The overall complexity of the solution is comparatively less with respect to the generic DSP based solution and much easier to modify for a different standard, when compared to the rigid ASIC based solution. The proposed solution is significantly different from the conventional way of designing the Base station with fixed ASICs and it clearly outweighs the solutions based on conventional approach in terms of flexibility, design complexity, design time and cost.

La génération d’aléa joue un rôle fondamental en cryptographie et en sécurité. Des nombres aléatoires sont nécessaires pour la production de clés cryptographiques ou de vecteurs d’initialisation et permettent également d’assurer que des protocoles d’échange de clé atteignent un niveau de sécurité satisfaisant. Dans la pratique, les bits aléatoires sont générés par un processus de génération de nombre dit pseudo-aléatoire, et dans ce cas, la sécurité finale du système dépend de manière cruciale de la qualité des bits produits par le générateur. Malgré cela, les générateurs utilisés en pratique ne disposent pas ou peu d’analyse de sécurité permettant aux utilisateurs de connaître exactement leur niveau de fiabilité. Nous fournissons dans cette thèse des modèles de sécurité pour cette analyse et nous proposons des constructions prouvées sûres et efficaces qui répondront à des besoins de sécurité forts. Nous proposons notamment une nouvelle notion de robustesse et nous étendons cette propriété afin d’adresser les attaques sur la mémoire et les attaques par canaux cachés. Sur le plan pratique, nous effectuons une analyse de sécurité des générateurs utilisés dans la pratique, fournis de manière native dans les systèmes d’exploitation (/dev/random sur Linux) et dans les librairies cryptographiques (OpenSSL ou Java SecureRandom) et nous montrons que ces générateurs contiennent des vulnérabilités potentielles. / In cryptography, randomness plays an important role in multiple applications. It is required in fundamental tasks such as key generation and initialization vectors generation or in key exchange. The security of these cryptographic algorithms and protocols relies on a source of unbiased and uniform distributed random bits. Cryptography practitioners usually assume that parties have access to perfect randomness. However, quite often this assumption is not realizable in practice and random bits are generated by a Pseudo-Random Number Generator. When this is done, the security of the scheme depends of course in a crucial way on the quality of the (pseudo-)randomness generated. However, only few generators used in practice have been analyzed and therefore practitioners and end users cannot easily assess their real security level. We provide in this thesis security models for the assessment of pseudo-random number generators and we propose secure constructions. In particular, we propose a new definition of robustness and we extend it to capture memory attacks and side-channel attacks. On a practical side, we provide a security assessment of generators used in practice, embedded in system kernel (Linux /dev/random) and cryptographic libraries (OpenSSL and Java SecureRandom), and we prove that these generators contain potential vulnerabilities.

The thesis deals with establishing uncertainties of indirect measurements. It focuses primarily on random number generators in software enabling the calculation of mea-surement uncertainties using Monte Carlo. Then it focuses on the uncertainty calculati-on indirect measurement as the Monte Carlo method and the classical numerical met-hod. The practical part deals with the verification of randomness generators numbers contained in various softwares. It also deals with the determination of uncertainties indi-rect current measurements by both above-mentioned methods and then comparing and evaluating the values achieved.

This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.