With the emergence of the Internet of Things (IoT), wireless body area networks (WBANs) are becoming increasingly pervasive in everyday life. Most WBANs are currently working at the IEEE 802.15.4 Zigbee standard. However there are growing interests to investigate the performance of BANs operating at higher frequencies (e.g. millimetre-wave band), due to the advantages offered compared to those operating at lower microwave frequencies. This thesis aims to realise printed conductive traces on flexible substrates, targeted for high frequency wearable electronics applications. Specifically, investigations were performed in the areas pertaining to the surface modification of substrates and the electrical performance of printed interconnects. Firstly, a novel methodology was proposed to characterise the dielectric properties of a non-woven fabric (Tyvek) up to 20 GHz. This approach utilised electromagnetic (EM) simulation to improve the analytical equations based on transmission line structures, in order to improve the accuracy of the conductor loss values in the gigahertz range. To reduce the substrate roughness, an UV-curable insulator was used to form a planarisation layer on a non-porous substrate via inkjet printing. The results obtained demonstrated the importance of matching the surface energy of the substrate to the ink to minimise the ink de-wetting phenomenon, which was possible within the parameters of heating the platen. Furthermore, the substrate surface roughness was observed to affect the printed line width significantly, and a surface roughness factor was introduced in the equation of Smith et al. to predict the printed line width on a substrate with non-negligible surface roughness (Ra ≤ 1 μm). Silver ink de-wetting was observed when overprinting silver onto the UV-cured insulator, and studies were performed to investigate the conditions for achieving electrically conductive traces using commercial ink formulations, where the curing equipment may be non-optimal. In particular, different techniques were used to characterise the samples at different stages in order to evaluate the surface properties and printability, and to ascertain if measurable resistances could be predicted. Following the results obtained, it was demonstrated that measurable resistance could be obtained for samples cured under an ambient atmosphere, which was verified on Tyvek samples. Lastly, a methodology was proposed to model for the non-ideal characteristics of printed transmission lines to predict the high frequency electrical performance of those structures. The methodology was validated on transmission line structures of different lengths up to 30 GHz, where a good correlation was obtained between simulation and measurement results. Furthermore, the results obtained demonstrate the significance of the paste levelling effect on the extracted DC conductivity values, and the need for accurate DC conductivity values in the modelling of printed interconnects.

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Le rendement consommation/fréquence des futures générations de circuits intégrés sur silicium n’est pas satisfaisant à cause de la faible mobilité électronique de ce semi-conducteur et des relativement grandes tensions d’alimentation VDD requises. Ce travail se propose d’explorer numériquement les potentialités des transistors à effet de champ (FET) à base de matériaux III-V à faible bande interdite et à haute mobilité pour un fonctionnement en haute fréquence et une ultra basse consommation. Tout d’abord, l’étude consiste à analyser théoriquement le fonctionnement d’une capacité MOS III-V en résolvant de façon auto-cohérente les équations de Poisson et Schrödinger (PS). On peut ainsi comprendre comment et pourquoi les effets extrinsèques comme les états de pièges à l’interface high-k/III-V dégradent les caractéristiques intrinsèques. Pour une géométrie 2D, les performances des dispositifs sont estimées pour des applications logiques et analogiques à l’aide d’un modèle de transport quasi-balistique.Nous avons ensuite étudié plus en détails les performances des MOSFET III-V en régimes statiques et dynamiques sous faible VDD, à l’aide du simulateur particulaire MONACO de type Monte Carlo. Les caractéristiques de quatre topologies de MOSFET ont été quantitativement étudiées, en termes de transport quasi-balistique, de courants statiques aux états passants et bloqués, de rendement fréquence/consommation et de bruit. Nous en tirons des conclusions sur l’optimisation de ces dispositifs. Enfin, l'étude comparative avec un FET à base de Si démontre clairement le potentiel des MOSFET III-V pour les applications à haute fréquence, à faible puissance de consommation et à faible bruit. / The optimal frequency performance/power-consumption trade-off is very difficult to achieve using CMOS technology because of low Si carrier mobility and relatively large supply voltage (VDD) required for circuit operation. The main objective of this work is to theoretically explore, in terms of operation frequency and power consumption, the potentialities of nano-MOSFET based on III-V materials with low energy bandgap and high electron mobility.First, this work analyzes theoretically the operation of a III-V MOS capacitor using self-consistent solution of Poisson - Schrödinger system equation. We can thus understand how and why the interface trap state densities at high-k/III-V interfaces degrade the intrinsic characteristics. For a 2D geometry, the performance of devices is estimated for digital and analog applications using a model of quasi-ballistic transport.Then, we estimated the performance of III-V MOSFET in static and dynamic regimes under low VDD, using MONACO a Monte Carlo simulator. The characteristics of four designs of III-V MOSFET have been studied quantitatively in terms of quasi-ballistic transport, DC current in ON and OFF states, frequency/consumption efficiency and optimum matching conditions of noise. We provide the guideline on the design optimization of the devices.Finally, the comparative study with Si-based devices clearly demonstrates the potentiality of III-V nano-MOSFET architectures for high-frequency and low-noise application under low operating power and even for low voltage logic.