abstract: As integrated technologies are scaling down, there is an increasing trend in the process,voltage and temperature (PVT) variations of highly integrated RF systems. Accounting for these variations during the design phase requires tremendous amount of time for prediction of RF performance and optimizing it accordingly. Thus, there is an increasing gap between the need to relax the RF performance requirements at the design phase for rapid development and the need to provide high performance and low cost RF circuits that function with PVT variations. No matter how care- fully designed, RF integrated circuits (ICs) manufactured with advanced technology nodes necessitate lengthy post-production calibration and test cycles with expensive RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast measurement of performance parameters during both post-production and in-eld op- eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip measurement of RF performance parameters. In this dissertation, three aspects of automated test and calibration, including DFT mathematical model, BIST hardware and built-in calibration are covered for RF front-end blocks. First, the theoretical foundation of a post-production test of RF integrated phased array antennas is proposed by developing the mathematical model to measure gain and phase mismatches between antenna elements without any electrical contact. The proposed technique is fast, cost-efficient and uses near-field measurement of radiated power from antennas hence, it requires single test setup, it has easy implementation and it is short in time which makes it viable for industrialized high volume integrated IC production test. Second, a BIST model intended for the characterization of I/Q offset, gain and phase mismatch of IQ transmitters without relying on external equipment is intro- duced. The proposed BIST method is based on on-chip amplitude measurement as in prior works however,here the variations in the BIST circuit do not affect the target parameter estimation accuracy since measurements are designed to be relative. The BIST circuit is implemented in 130nm technology and can be used for post-production and in-field calibration. Third, a programmable low noise amplifier (LNA) is proposed which is adaptable to different application scenarios depending on the specification requirements. Its performance is optimized with regards to required specifications e.g. distance, power consumption, BER, data rate, etc.The statistical modeling is used to capture the correlations among measured performance parameters and calibration modes for fast adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by embedding built-in tuning knobs in LNA design in 130nm technology. The tuning knobs are carefully designed to provide independent combinations of important per- formance parameters such as gain and linearity. Minimum number of switches are used to provide the desired tuning range without a need for an external analog input. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

A significant growth was witnessed in the field of Wireless Sensor Networks (WSNs), in the previous decade. The objective of this study has been Survey of micro controllers and short-range radio transceivers for wireless sensors and provide an extensive overview of micro controllers and RF-transceivers in the Market and compare the relevant properties for designing wireless sensor nodes. In the survey, RF-transvers from Nordic semiconductors is extensively presented for short-rang wireless protocols some of the protocols are RF-Communication Module, Bluetooth Low Energy Module, ZigBee module and Wi-Fi module.          In WSNs node design Power consumption is one the most important design issue, this thesis work present the different type of WSN protocols energy consumption efficiency and power consumption, compared and conclude graphically.        Microcontrollers are the main part of WSNs node for processing and gathering sensor data. There is different microcontroller’s products in the market however the WSN protocols presented in this thesis uses Cortex-M4 processor which is one of ARM product, the specification and comparison of this product with other products is presented.

With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs. / text