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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A Area-Saving ROM Decoder and Design of Network Interface Controller

Chen, Ying-Pei 26 June 2000 (has links)
The thesis is composed of two different IC design projects, which are briefly introduced as follows. The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology. The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.
2

Hardware Implementation of Plasma Display Panel Data Dispatcher and Fast Bipolar-valued Inner Product Processor

Hsueh, Ya-Hsin 05 October 2004 (has links)
In this thesis, we firstly present a low-cost plasma display panel (PDP) data dispatcher for image enhancement. By taking advantage of the proposed ADS method with 10 subfields and data reordering, our design can reduce 20% of the PDP dispatcher cost and resolve the ¡§dynamic false contour¡¨ problem. Secondly, a bipolar-valued inner product processor for associative memory neural networks is proposed to compute the inner product of two bipolar-valued vectors. Our analysis shows that the delay of inner product is reduced significantly from O(2n) to O(n). We also propose a 3-dimensional address decoding structure associated with a corresponding data cell encoding arrangement for P+implant ROMs such that the data words are encoded and stored in the ROMs in a natural pattern. Not only is the size of the entire decoder shrunk, the access time and power dissipation is also greatly reduced, which is very suitable to be utilized in implantable devices. Finally, we introduce a multi-parameter implantable neural interface micro-stimulator system, including the external control module, the protocol, and the SOC (system-on-chip) chip. The proposed system is expected to carry out the externally given commands to stimulate the corresponding neural trunks. On the other way around, it can sense and deliver the response of the neural trunks to an external monitoring device in the future.

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