As the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows. / text

The research attempts to provide a graphical theory-based approach to solve the facility layout problem. Which has generally been approached using Quadratic Assignment Problem (QAP) in the past, an algebraic method. It is a very complex problem and is part of the NP-Hard optimization class, because of the nonlinear quadratic objective function and (0,1) binary variables. The research is divided into three phases which together provide an optimal facility layout, block plan solution consisting of MHS (material handling solution) projected onto the block plan. In phase one, we solve for the position of departments in a facility based on flow and utility factor (weight for location). The position of all the departments is identified on the vertices of MPG (maximal planar graph), which maximizes the possibility of flow. We use named MPG produced in literature, throughout the research. The grouping of the department is achieved through GMAFLAD, a QSP (quadratic set packing) based optimizer. In Phase 2, the dual for the MPG’s is solved consisting of department location as per phase 1, to generate Voronoi graphs. These graphs are then, expanded by an ingenious parameter optimization formulation to achieve area fitting for individual cases. Optimization modeling software, Lingo17.0 is used for solving the parameter optimization for generating coordinates of the block plan. The plotting of coordinates for the block plan graphics is done via Autodesk inventor 2019. In phase 3, the solution for MHS is achieved using an RSMT (Rectilinear Steiner minimal tree) graph approach. The Voronoi seed coordinates produced through phase 2 results are computed by GeoSteiner package to generated the RSMT graph for projection onto the block plan (Also, done by Inventor 2019). The graphical method employed in this research, itself has complex and NP-hard problem segments in it, which have been relaxed to polynomial time complexity by fragmenting into groups and solving them in sections. Solving for MPG & RSMT are a class of NP-Hard problem, which have been restricted to N=32 here. Finally, to validate the research and its methodology a real-life case study of a shipyard building for the data set of PDVSA, Venezuela is performed and verified.