The widespread use of microprocessor chips in high performance applications like graphics simulators and low power applications like mobile phones, laptops, medical applications etc. has made power estimation an important step in the manufacture of VLSI chips. It has become necessary to estimate the power consumption not only after the circuits have been laid out, but also during the design of the modules of the microprocessor at higher levels of design abstraction. The design of a microprocessor is complex and is performed at multiple layers of abstraction before it finally gets manufactured. The processor is first conceptually designed using blocks at the system level, and then modeled using a high-level language (C, C++, SystemC). This enables the early development of software applications using these high-level models. The C/C++ model is then translated to a hardware description language (HDL), that typically corresponds to the register transfer level (RT-Level). Once the processor is defined at the RT-Level, it is synthesized into gates and state elements based on user-defined constraints. In this thesis, novel techniques to estimate the power consumed by the microprocessor circuits at the gate level and RT-level of abstraction are presented. At the gate level, the average power consumed by microprocessor circuits is straight-forward to estimate, as the implementation is known. However, estimating the maximum or peak instantaneous power consumed by the microprocessor as a whole, when it is executing instructions, is a hard problem due to the high complexity of the state space involved. An hierarchical approach to estimate the peak power using powerful search techniques and formal tools is presented in this thesis. This approach has been extended and applied to solve the problem of estimating the maximum supply drop. Details on this extension and a discussion of promising results are also presented. In addition, this approach has been applied to explore the possibility of minimizing the leakage component of power dissipation, when the processor is idle. At the register transfer level, estimating the average power consumed by the circuits of the microprocessor is by itself a challenging problem. This is due to the fact that their implementation is unknown at this level of abstraction. The average power consumption directly depends on the implementation. The implementation, in turn, depends on the performance constraint imposed on the microprocessor. One of the factors affecting the performance of the microprocessor, is the speed of operation of its circuits. Considering these factors and dependencies (for making early design decisions at the RT-Level), a methodology that estimates the power vs. delay curves of microprocessor circuits has been developed. This will enable designers to make design decisions for even rudimentary designs without going through the time consuming process of synthesis. / text

<p>In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. </p><p>Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.</p>

In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.