High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012

M.Ing. / The increase of interest in the development of radio communications, both terrestrial and satellite is reaching far and beyond the most optimistic expectations. There has been an accelerated emergence of newer technologies, all claiming highly coveted radio frequency spectrum resources. With the push for the development of location based services, utilizing satellite com- communications for military purposes and later for civilian use; there has been a parallel development in terrestrial communications technology making it possible to implement cost efficient reliable user systems for voice and data services ...

Hon Kwok-Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1. --- System Architecture --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Receiver Architectures --- p.2 / Chapter 1.2.1 --- Superheterodyne Receiver --- p.2 / Chapter 1.2.2 --- Homodyne Receiver --- p.3 / Chapter 1.2.3 --- Image-Reject Receiver --- p.5 / Chapter 1.2.4 --- Low intermediate frequency Receiver --- p.7 / Chapter 1.3 --- Double Intermediate Frequency Receivers --- p.8 / Chapter 1.3.1 --- Introduction --- p.8 / Chapter 1.3.2 --- Background Theory --- p.8 / Chapter 2. --- Receiver Fundamentals --- p.23 / Chapter 2.1 --- Noise model --- p.23 / Chapter 2.1.1 --- Thermal noise of resistors --- p.23 / Chapter 2.1.2 --- Channel noise of transistors --- p.24 / Chapter 2.2 --- Noise Figure --- p.26 / Chapter 2.3 --- Linearity --- p.26 / Chapter 2.3.1 --- 1 -dB Compression point --- p.27 / Chapter 2.3.2 --- Third Intercept point (IP3) --- p.28 / Chapter 2.3.3 --- Dynamic Range (DR) --- p.30 / Chapter 2.3.3.1 --- Spurious-Free Dynamic Range (SFDR) --- p.30 / Chapter 2.3.3.2 --- Blocking Dynamic Range (BDR) --- p.32 / Chapter 3. --- Spiral Inductor --- p.33 / Chapter 3.1 --- Spiral inductor modeling --- p.34 / Chapter 3.2 --- Spiral Inductor model parameters --- p.36 / Chapter 3.3 --- Characteristic of spiral inductor --- p.36 / Chapter 3.4 --- Inductor Design and Optimization --- p.37 / Chapter 4. --- Low Noise Amplifier (LNA) --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Common LNA Architectures --- p.39 / Chapter 4.2.1 --- Resistive Termination --- p.39 / Chapter 4.2.2 --- 1/gm Termination --- p.42 / Chapter 4.2.3 --- Shunt-Series Feedback --- p.43 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.43 / Chapter 4.3 --- Full Schematic diagram of the Low Noise Amplifier --- p.45 / Chapter 4.4 --- Full noise analysis of the LNA using inductive source degeneration --- p.46 / Chapter 4.4.1 --- Output noise due to channel noise --- p.46 / Chapter 4.4.1.1 --- Output noise due to i2d --- p.47 / Chapter 4.4.1.2 --- "Output noise due to i2g,u" --- p.47 / Chapter 4.4.1.3 --- "Output noise due to i2g,c and i2d" --- p.49 / Chapter 4.4.2 --- "Output noise due to Rg R,l Rs" --- p.51 / Chapter 4.4.3 --- Noise factor calculation --- p.52 / Chapter 4.4.3.1 --- Rl calculation --- p.52 / Chapter 4.4.3.2 --- Rg calculation --- p.52 / Chapter 4.4.3.3 --- Ql calculation --- p.53 / Chapter 4.4.3.4 --- wT calculation --- p.53 / Chapter 4.4.3.5 --- x calculation --- p.53 / Chapter 4.5 --- Simulation Result of the low noise amplifier (100 finger gate poly) --- p.54 / Chapter 4.5 --- Experimental Result of the low noise amplifier (100 finger gate poly) --- p.56 / Chapter 5. --- Down-conversion Mixer --- p.58 / Chapter 5.1 --- Introduction --- p.58 / Chapter 5.2 --- Gilbert Cell Mixer --- p.59 / Chapter 5.2.1 --- Circuit Description --- p.59 / Chapter 5.2.2 --- Basic Operation --- p.60 / Chapter 5.2.3 --- Simulation Result of the Gilbert Cell Mixer --- p.62 / Chapter 5.3 --- Single-ended to Differential-ended Converter --- p.66 / Chapter 5.3.1 --- Simulation Result of the Single-Ended to Differential-Ended Converter --- p.68 / Chapter 5.4 --- Experimental Result of The Gilbert Cell Mixer --- p.70 / Chapter 5.4.1 --- 1-dB compression point experiment --- p.70 / Chapter 5.4.2 --- IIP3 experimental setup and result --- p.72 / Chapter 5.4.3 --- "Experimental result of 1 -dB compression point, IIP3, conversion gain, SFDR and BDR" --- p.74 / Chapter 5.4.4 --- LO power verse conversion gain --- p.75 / Chapter 5.4.5 --- Intermediate frequency verse conversion gain --- p.77 / Chapter 5.4.6 --- Experimental result of input matching and isolation --- p.78 / Chapter 6. --- Asymmetric Polyphase Network --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Performance of the Asymmetric Polyphase Network --- p.81 / Chapter 6.2.1 --- First Building Block --- p.82 / Chapter 6.2.2 --- Second Building Block --- p.83 / Chapter 6.2.3 --- Third Building Block --- p.84 / Chapter 6.2.4 --- Forth Building Block --- p.84 / Chapter 6.3 --- Simulation result of the asymmetric polyphase network --- p.85 / Chapter 6.4 --- Experimental result of the asymmetric polyphase network --- p.86 / Chapter 7. --- Conclusion --- p.87 / Chapter 8. --- Reference --- p.89 / Chapter 9. --- Appendix A --- p.92 / Chapter 10. --- Appendix B --- p.95 / Chapter 11. --- Appendix C --- p.98 / Chapter 12. --- Appendix D --- p.99

Graduation date: 1999

The wide bandwidth employed in the UWB system allows for high data-rate communications, while its broadband nature requires it to coexist with other systems. For instance, several communication systems, such as digital TV, wireless LANs, WiMAX, and satellite receivers, utilize spectrum that is in the UWB band. According to Federal Communications Commission (FCC) regulations, the power spectral density (PSD) of UWB devices for communication applications is limited to less than -41.25dBm/MHz in the 3.1-10.6GHz frequency band, to minimize the impact of UWB on other systems. The impact of narrowband signals on UWB systems can also be significant, even though these signals may occupy a small part of the UWB spectrum, due to their much larger power. The performance and capacity of UWB systems can be significantly degraded by these narrowband interferers. In-band interference can be tolerated by increasing the dynamic-range of the receiver such that the interferers are accommodated within the linear range of the receiver. Alternatively, if the interferers can be avoided altogether, the excessive linearity requirements imposed by the interferers can be relaxed. Such an avoidance mechanism requires the ability to detect interferers. This work presents a low-power and low-cost detector for this purpose that can be employed in multi-band approaches to UWB, including pulse-based schemes, and those employing OFDM. The UWB band is divided into narrower sub-bands in these schemes. During transmission, the carrier hops to a new sub-band every symbol. The detector is designed to provide a profile of interference over the entire UWB spectrum, during each symbol period. This information would be available to the main-path UWB receiver to decide a frequency sequence of sub-band hopping, in order to avoid sub-bands occupied by large interferers. This relaxes the dynamic-range requirement, and hence the power dissipation of the main-path receiver, thus compensating for the extra power dissipation of the detector. The detector is based on a cascade of image-reject downconverter stages. An implementation of the architecture is demonstrated in a 0.13[mu]m CMOS process. / text

The application of digital signal processing to radio communications has come of age with the advent of low power, high speed microprocessors and over the past five years, various transceiver architectures, utilizing this new technology have been extensively researched. Due to the flexible nature of a software based transceiver, a myriad of possible applications exist and currently the emphasis is on the development of suitable algorithms. The principal aim of this research is the derivation of optimized digital signal processing algorithms applicable to three separate areas of radio communications. Optimized, as used by the author within this dissertation, implies a reasonable compromise between performance, complexity and numerical processing efficiency. This compromise is necessary since the algorithms are applied to a portable transceiver where power consumption, size and weight are limited. The digital signal processing algorithms described by this research is as follows:- 1. The derivation and assessment of a multirate speech amplitude modulation demodulator which exhibits low distortion (typically less than 2%) for a wide range of modulation indices, carrier frequency offsets and deviations. The demodulator is processing efficient and requires only five multiplications and five decisions for every output sample. 2. The derivation and assessment of a low sampling rate speech frequency modulation demodulator for signals whose bandwidth exceed quarter the sampling frequency. The demodulator exhibits low distortion (typically less than 2%) and is processing efficient requiring eighteen multiplications and three decisions for every output sample. 3. The derivation and assessment of a multirate single-sideband suppressed carrier automatic frequency control system which is a combination of a simple second order adaptive line enhancer and a digital phase-locked loop. The processing efficient automatic frequency control system is suited for low signal to noise power conditions, in both stationary and mobile communication channels. / Thesis (Ph.D.)-University of Natal, Durban, 1992.

This thesis discusses the design, fabrication, integration and characterization of millimeter wave passive components using polymer-core-conductor surface micromachining technologies. Several antennas, including a W-band broadband micromachined monopole antenna on a lossy glass substrate, and a Ka-band elevated patch antenna, and a V-band micromachined horn antenna, are presented. All antennas have advantages such as a broad operation band and high efficiency. A low-loss broadband coupler and a high-Q cavity for millimeter-wave applications, using surface micromachining technologies is reported using the same technology. Several low-loss all-pole band-pass filters and transmission-zero filters are developed, respectively. Superior simulation and measurement results show that polymer-core-conductor surface micromachining is a powerful technology for the integration of high-performance cavity, coupler and filters. Integration of high performance millimeter-wave transceiver front-end is also presented for the first time. By elevating a cavity-filter-based duplexer and a horn antenna on top of the substrate and using air as the filler, the dielectric loss can be eliminated. A full-duplex transceiver front-end integrated with amplifiers are designed, fabricated, and comprehensively characterized to demonstrate advantages brought by this surface micromachining technology. It is a low loss and substrate-independent solution for millimeter-wave transceiver integration.

Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: John Papapolymerou; Committee Chair: Manos Tentzeris; Committee Member: Gordon Stuber; Committee Member: John Cressler; Committee Member: John Z. Zhang; Committee Member: Joy Laskar

Light, as a medium for communication, has the unique ability to transmit volumes of data with minimal energy loss. This capability not only sparked the revolution of internet-based communication over fiber optic networks, but also holds the potential to expand computing beyond our current capabilities. At present, data is stored densely in computer chips, but is sent out of the chip through centimeter-long electrical wires in a slow and energy-intensive process, before finally interfacing with optical transmitters. To bypass this bottleneck, electrical channels can be condensed and converted into light over a compact area using integrated photonic chips. In particular, the silicon photonics technology platform offers the potential for extremely dense data communications due to its high confinement waveguides and compact micro-resonators. However, three major obstacles stand in the way of realizing a low-energy and bandwidth-dense implementation of this technology: the integration of photonics with electronics, optical coupling from the photonic chip to fiber, and scaling up link architectures to multiplex data streams onto many wavelengths. The work in this thesis aims to confront these three challenges and advance integrated photonics technology to unprecedented bandwidth densities and energy efficiencies, with a focus on the first challenge of photonic-electronic integration. It begins with an overview of the escalating demand for inter-chip bandwidths and the potential solution offered by integrated photonics. Next, this thesis builds a theoretical framework for the performance parameters and sources of energy consumption that are addressed in the subsequent sections. After this introductory context, the thesis describes the achievement of the highest density and largest scale photonic-electronic integration to date, using a dense, 25 um pitch 3D bonding process. An 80-channel array fabricated in this integration records the lowest data link energies to date, at 120 fJ/bit, and transfers data at 10 Gbit/s/channel for a record 5.3 Tbit/s/mm2 bandwidth density. The discussion then shifts to the issue of chip-to-fiber coupling efficiency, traditionally the greatest source of loss in photonic links. A substrate-removed edge coupler design reduces this loss to a mere 1.1 dB, and an inverse-designed edge coupler taper shows a fourfold length reduction compared to linear tapers. Lastly, the thesis presents designs for wavelength scaling that increase the number of energy efficient channels on a single fiber. Specifically, it demonstrates a multi-channel, polarization diverse micro-comb receiver and a 3D-integrated transceiver with wavelength interleaving to waveguide buses of cascaded resonators. This thesis builds on photonic device developments to introduce photonic systems with the lowest energy and densest data communications to date. Together, these results unlock the tremendous potential of light as a fast and energy-efficient communication medium between chips, paving a sustainable path towards scaling artificial intelligence and disaggregating computation and memory resources.

This research aims at solving an engineering design problem encountered in the field of wireless communication systems using mathematical programming techniques. The problem addressed is an indispensable part of micro-cellular radio system design. It involves an optimal location of radio transmitters, given a distribution of receivers and desired signal characteristics. The study has been conducted with the intent of making this problem an integral part of a CAD system for designing radio communication systems. The tool that has been developed for locating a transmitter in such a context is sensitive to different needs of coverage at different locations in the design space. The physical nature of this problem enables it to be conceptualized as a traditional facility location problem. The transmitter is a service facility responsible for serving all the receivers in the design space. A cost is incurred in terms of path-loss, delay spread, and other separation-based measures, whenever service is extended to a receiver. The objective is to place this transmitter in such a way that it optimally serves all the receivers, as measured according to some merit function. However, the nature of the latter merit or objective function, and the nature of the acceptable region for transmitter placement, imparts a special structure to the problem that distinguishes it from traditional facility location problems. The aim of this research effort is to construct a suitable representative mathematical model for this problem, and to design and compare various solution methodologies that are computationally competitive, numerically stable, and accurate. / Master of Science