The goal of this research is to present a framework to accelerate the execution of software legacy systems without having to redesign them or limit future changes. The speedup is accomplished through hardware acceleration, based on a semi-automatic infrastructure which supports design decisions and simulate their impact. Many programs are available for translating code written in C into VHDL (Very High Speed Integrated Circuit Hardware Description Language). What is missing is simpler and more direct strategies to incorporate encapsulatable portions of the code, translate them to VHDL and to allow the VHDL code and the C code to communicate through a flexible interface. SHARP is a streamlined, easily understood infrastructure which facilitates this process in two phases. In the first part, the SHARP GUI (An interactive Graphical User Interface) is used to load a program written in a high level general purpose programming language, to scan the code for SHARP POINTs (Portions Only Including Non-interscoping Types) based on user defined constraints, and then automatically translate such POINTs to a HDL. Finally the infrastructure needed to co-execute the updated program is generated. SHARP POINTs have a clearly defined interface and can be used by the SHARP scheduler. In the second part, the SHARP scheduler allows the SHARP POINTs to run on the chosen reconfigurable hardware, here an FPGA (Field Programmable Gate Array) and to commu- nicate cleanly with the original processor (for the software). The resulting system will be a good (though not necessarily optimal) acceleration of the original software application, that is easily maintained as the code continues to develop and evolve. / Graduate