Jitter is defined as timing uncertainties of digital signals at their intended ideal positions in time. While it undermines valuable clock budget and limits the maximum clock frequency in I/O circuitry, it is one of the most difficult parameters to measure accurately due to the small value and randomness. This thesis proposes a random jitter RMS measurement method using AND and OR operations, which targets BIST applications. This thesis is organized as follows. Chapter 1 introduces the motivation of the proposed work. It includes a comparison between two major approaches to jitter measurement. Chapter 2 explains the proposed random jitter estimation method in detail. Chapter 3 describes circuit implementations with design considerations. Chapter 4 demonstrates estimation results from circuit level simulation runs. Chapter 5 discusses the source of error in the jitter estimation and concludes. / text

摘要 本文主要在探討絕對正則隨機變數序列的隨機修剪L統計量的漸近性，當修剪係系數收斂至a和b時(O<a<b<l)，對它們的分配函數限制並不多；然而當a=0及b=1 時，則限制的條件須更加嚴格，這也就是為什麼我們要做隨機修剪的主要原因。同時，由於大部分的時間序列模式都是絕對正則的隨機變數序列，這也是研究本文的主要動機之一。 本文是想嘗試著把G. R. Shorack (1989)的論文隨機修剪L統計量，推廣，把該文中立相獨立的隨機變數序列換成絕對正則的隨機變數序列。在這同時，我們必需將一些經驗累積分配函數的不等式推廣，推廣過程中將重覆使用Yoshihara (1978) 的機率不等式。 / ABSTRACT We will prove central limit theorem for randomly trimmed L-statistics with absolutely regular random variables. When the fractions trimmed converge to a and l-b, (with 0<a<b<l) there are little restrictions on the df's of the r.v.'s, - but the limiting r.v. has several contributing terms, making the studentization complicated unless the trimming fractions converge fast enough. For a=0 and b=l, the restriction on the rate of convergence of the trimming fractions is more severe, however this is a most reasonable way to trim.

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