The basic idea deals with detecting the voltage collapse ahead of time to provide the operators a lead time for remedial actions and for possible prevention of blackouts. To detect cases of voltage collapse, we shall create methods using pattern recognition in conjunction with real time simulation of case studies and shall develop heuristic methods for separating voltage stable cases from voltage unstable cases that result in response to system contingencies and faults. Using Real Time Simulator in Entergy-UNO Power & Energy Research Laboratory, we shall simulate several contingencies on IEEE 39-Bus Test System and compile the results in two categories of stable and unstable voltage cases. The second stage of the proposed work mainly deals with the study of different patterns of voltage using artificial neural networks. The final stage deals with the training of the controllers in order to detect stability of power system in advance.

A real-time simulator (RTS) with digital and analog input/output modules is used to conduct hardware-in-the-loop simulations to evaluate performance of power system equipment such as protective relays by exposing the equipment to the simulated realistic operating conditions. This work investigates the use of RTS to test relays with single-pole-switching (SPS) feature. Single-pole switching can cause misoperations due to fault arc during reclosing of the breakers. Through this investigation, a test procedure appropriate for the testing SPS relays has been developed. The test procedure includes power system modeling for real time simulation, relay test setup, and test plan. HYPERSIM real-time simulator was used to model an actual power system. Transmission lines, three-winding transformers, and induction motor were modeled with actual parameters. Models for fault arc in HYPERSIM real time simulator were developed. Test set-up for evaluating relay performance and wiring drawings for connecting relay in closed-loop to the simulator were developed.

The South African National Defence Force (SANDF) currently requires a system of systems simulation capability for supporting the different phases of a Ground Based Air Defence System (GBADS) acquisition program. A non-distributed, fast-as-possible simulator and its architectural predecessors developed by the Council for Scientific and Industrial Research (CSIR) was able to provide the required capability during the concept and definition phases of the acquisition life cycle. The non-distributed simulator implements a 100Hz logical time Discrete Time System Specification (DTSS) in support of the existing models. However, real-time simulation execution has become a prioritised requirement to support the development phase of the acquisition life cycle. This dissertation is about the ongoing migration of the non-distributed simulator to a practical simulation architecture that supports the real-time requirement. The simulator simulates a synthetic environment inhabited by interacting GBAD systems and hostile airborne targets. The non-distributed simulator was parallelised across multiple Commod- ity Off the Shelf (COTS) PC nodes connected by a commercial Gigabit Eth- ernet infrastructure. Since model reuse was important for cost effectiveness, it was decided to reuse all the existing models, by retaining their 100Hz logical time DTSSs. The large scale and event-based High Level Architecture (HLA), an IEEE standard for large-scale distributed simulation interoperability, had been identified as the most suitable distribution and parallelisation technology. However, two categories of risks in directly migrating to the HLA were iden- tified. The choice was made, with motivations, to mitigate the identified risks by developing a specialised custom distributed architecture. In this dissertation, the custom discrete time, distributed, peer-to-peer, message-passing architecture that has been built by the author in support of the parallelised simulator requirements, is described and analysed. It reports on empirical studies in regard to performance and flexibility. The architecture is shown to be a suitable and cost effective distributed simulator architecture for supporting a speed-up of three to four times through parallelisation of the 100 Hz logical time DTSS. This distributed architecture is currently in use and working as expected, but results in a parallelisation speed-up ceiling irrespective of the number of distributed processors. In addition, a hybrid discrete-time/discrete-event modelling approach and simulator is proposed that lowers the distributed communication and time synchronisation overhead—to improve on the scalability of the discrete time simulator—while still economically reusing the existing models. The pro- posed hybrid architecture was implemented and its real-time performance analysed. The hybrid architecture is found to support a parallelisation speed- up that is not bounded, but linearly related to the number of distributed pro- cessors up to at least the 11 processing nodes available for experimentation. / Dissertation (MSc)--University of Pretoria, 2009. / Computer Science / unrestricted

“Hardware in the Loop” (HIL) testing is widely used in the automotive industry. The sophisticated electronic control units used for vehicle control are usually tested and evaluated using HIL-simulations. The HIL increases the degree of realistic testing of any system. Moreover, it helps in designing the structure and control of the system under test so that it works effectively in the situations that will be encountered in the system. Due to the size and the complexity of interaction within a power network, most research is based on pure simulation. To validate the performance of physical generator or protection system, most testing is constrained to very simple power network. This research, however, examines a method to test power system hardware within a complex virtual environment using the concept of the HIL. The HIL testing for electronic control units and power systems protection device can be easily performed at signal level. But performance of power systems equipments, such as distributed generation systems can not be evaluated at signal level using HIL testing. The HIL testing for power systems equipments is termed here as ‘Power Network in the Loop’ (PNIL). PNIL testing can only be performed at power level and requires a power amplifier that can amplify the simulation signal to the power level. A power network is divided in two parts. One part represents the Power Network Under Test (PNUT) and the other part represents the rest of the complex network. The complex network is simulated in real time simulator (RTS) while the PNUT is connected to the Voltage Source Converter (VSC) based power amplifier. Two way interaction between the simulator and amplifier is performed using analog to digital (A/D) and digital to analog (D/A) converters. The power amplifier amplifies the current or voltage signal of simulator to the power level and establishes the power level interaction between RTS and PNUT. In the first part of this thesis, design and control of a VSC based power amplifier that can amplify a broadband voltage signal is presented. A new Hybrid Discontinuous Control method is proposed for the amplifier. This amplifier can be used for several power systems applications. In the first part of the thesis, use of this amplifier in DSTATCOM and UPS applications are presented. In the later part of this thesis the solution of network in the loop testing with the help of this amplifier is reported. The experimental setup for PNIL testing is built in the laboratory of Queensland University of Technology and the feasibility of PNIL testing has been evaluated using the experimental studies. In the last section of this thesis a universal load with power regenerative capability is designed. This universal load is used to test the DG system using PNIL concepts. This thesis is composed of published/submitted papers that form the chapters in this dissertation. Each paper has been published or submitted during the period of candidature. Chapter 1 integrates all the papers to provide a coherent view of wide bandwidth switching amplifier and its used in different power systems applications specially for the solution of power systems testing using PNIL.

Doctor of Philosophy / Electrical and Computer Engineering / Anil Pahwa / Noel N. Schulz / Microgrids with distributed generators have changed how protection and control systems are designed. Protection systems in conventional U.S. distribution systems are radial with the assumption that current flows always from the utility source to the end user. However, in a microgrid with distributed generators, currents along power lines do not always flow in one direction. Therefore, protection systems must be adapted to different circuit paths depending on distributed generator sites in the microgrid and maximum fuse ampere ratings on busses. Adaptive overcurrent protection focuses on objectives and constraints based on operation, maximum load demand, equipment, and utility service limitations. Adaptive overcurrent protection was designed to protect the power lines and bus feeders of the microgrid with distributed generators by coordinating fuses and relays in the microgrid. Adaptive overcurrent protection was based on the relay setting group and protection logic methods. Non-real-time simulator (NRTS) and real-time simulator (RTS) experiments were performed with computer-based simulators. Tests with two relays in the loop proved that primary relays tripped faster than backup relays for selectivity coordination in the adaptive overcurrent protection system. Relay test results from tripping and non-tripping tests showed that adaptive inverse time overcurrent protection achieved selectivity, speed, and reliability. The RTS and NRTS with two relays in the loop techniques were described and compared in this work. The author was the first graduate student to implement real-time simulation with two relays in the loop at the Burns & McDonnell - K-State Smart Grid Laboratory. The RTS experimental circuit and project are detailed in this work so other graduate students can apply this technique with relays in the loop in smart grid research areas such as phasor measurement units, adaptive protection, communication, and cyber security applications.

L’objectif de ce travail de Thèse est d’évaluer les capacités de composants numérique de type Système-sur-Puce (SoC en anglais) pour l’implantation de Simulateurs Temps Réel Embarqués (ERTS en anglais) de systèmes électromécaniques et d’électronique de puissance. En effet, l’utilisation de ces simulateurs n’est pas seulement limitée aux validations matériel dans la boucle (en anglais Hardware-in-the-Loop ou HIL) du système mais doivent également être embarqués avec le contrôleur afin d’assurer plusieurs fonctionnalités additionnelles comme l'observation, l'estimation, commande sans capteur (ou sensorless), le diagnostic ou la surveillance de la santé, commande tolérante aux défauts, etc.La réalisation de ces simulateurs doit néanmoins considérer plusieurs contraintes à plusieurs niveaux de développement : durant la modélisation de la partie du système à simuler en temps-réel, durant la réalisation numérique et enfin durant l’implantation sur le composant numérique utilisé. Ainsi, le travail réalisé durant cette Thèse s’est focalisé sur ce dernier niveau et l’objectif était d’évaluer les capacités temps/ressources des composants de type SoC pour l’implantation de modules ERTS. Ce type de plateformes intègrent dans un même composant de puissants processeurs, un circuit logique programmable (de type Field-Programmable Gate Array ou FPGA), et d’autres périphériques, ce qui offre plusieurs opportunités d’implantation.Afin de pallier les limitations liées au codage VHDL de la partie FPGA, il existe des outils High-Level Synthesis (HLS) qui permettent de programmer ces dispositifs en utilisant des langages à haut niveau d'abstraction comme C, C++ ou SystemC. De plus, en incluant des directives et contraintes au code source, ces outils peuvent produire des implémentations matérielles différentes (architecture totalement combinatoire, « pipeline », architecture parallélisées ou factorisées, arranger les données et leurs formats pour une meilleure utilisation des ressources de mémoire, etc.).Dans le but d’évaluer ces différentes implantations, deux cas d’études ont été choisis : le premier se compose d’un Générateur Asynchrone à Double Alimentation (GADA) et le second d’un Convertisseur Modulaire Multiniveau (ou Modular Multi-level Converter - MMC). Vu que la GADA a une dynamique basse/moyenne (dynamiques électriques et mécaniques), deux versions d’implantations ont été évaluées : (i) une implantation full-software en utilisant seulement les processeurs ARM; et (ii) une implantation full-hardware en utilisant l’outil HLS pour programmer la partie FPGA. Ces deux versions ont été évaluées avec différentes optimisations du compilateur et trois formats de données: 64/32-bit en virgule flottante, et 32-bit en virgule flottante. L’approche mixe software/hardware a également été évaluée à travers la caractérisation des transferts de données entre le processeur et l’IP ERTS implantée dans la partie FPGA. Quant au convertisseur MMC, sa complexité et sa forte dynamique (dynamique de commutation) impose une implantation exclusivement full-hardware. Celle-ci a également été réalisée à base d’outils HLS.Enfin pour la validation expérimentale de ce travail de Thèse, une maquette à base de convertisseur MMC a été construite dans le but de comparer des mesures du système réel avec les résultats fournis par l’IP ERTS. / This Doctoral Thesis is a detailed study of how suitable System-on-Chip (SoC) devices are for implementing Embedded Real-Time Simulators (ERTS) of electromechanical and power electronic systems. This emerging class of Real-Time Simulators (RTS) are not only expected for Hardware-in-the-Loop (HIL) validations of systems; but they also have to be embedded within the controller to play several roles like observers, parameter estimation, diagnostic, health monitoring, fault-tolerant and sensorless control, etc.The design of these Intellectual Properties (IP) must rigorously consider a set of constraints at different development stages: (i) during the modeling of the system to be real-time simulated; (ii) during the digital realization of the IP; and also (iii) during its final implementation in the digital platform. Thus, the conducted work of this Thesis focuses specially on this last stage and its aim is to evaluate the time/resource performances of recent SoC devices and study how suitable they are for implementing ERTSs. These kind of digital platforms combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling and monitoring a complete system.One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which needs extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ or SystemC. Moreover, by inserting directives and constraints to the source code, these tools can produce different hardware implementations (e.g. full-combinatorial design, pipelined design, parallel or factorized design, partition or arrange data for a better utilisation of memory resources, etc.).This dissertation is based on the implementation of two representative applications that are well known in our laboratory: a Doubly-fed Induction Generator (DFIG) commonly used as wind turbines; and a Modular Multi-level Converter (MMC) that can be arranged in different configurations and utilized for many different energy conversion purposes. Since the DFIG has low/medium system dynamics (electrical and mechanical ones), both a full-software implementation using solely the ARM processor and a full-hardware implementation using HLS to program the FPGA will be evaluated with different design optimizations and data formats (64/32-bit floating-point and 32-bit fixed-point). Moreover, it will also be investigated whether a system of these characteristics is interesting to be run as a hardware accelerator. Different data transfer options between the Processor System (PS) and the Programmable Logic (PL) have been studied as well for this matter. Conversely, because of its harsh dynamics (switching dynamics), the MMC will be implemented only with a full-hardware approach using HLS tools, as well.For the experimental validation of this Thesis work, a complete MMC test bench has been built from scratch in order to compare the real-world results with its SoC ERTS implementation.

Nous proposons dans cette thèse, différents outils de réglage de tension et de gestion de la puissance réactive en fonction des conditions de raccordement des éoliennes au réseau électrique. Trois cas figure sont étudiés : raccordement direct sur un poste source de distribution, raccordement des éoliennes réparties dans un réseau de distribution et raccordement d’un ensemble de parcs éoliens au réseau de transport.Un algorithme de réglage basé sur l’asservissement de la puissance réactive est proposé pour le raccordement direct d'un parc sur un poste source. Un réglage coordonné de tension en présence de régleur en charge est proposé (D-RCT) pour le raccordement des éoliennes reparties dans un réseau de distribution. On propose aussi une version plus décentralisée du réglage coordonné (D2-RCT) qui pourrait être implantée sous forme de système multi-agents intelligents (SMA). Un system de control multi-niveaux est proposé pour le raccordement d’un ensemble de parcs éoliens au réseau de transport. Il permet de répondre de manière optimale à une demande puissance réactive envoyée par le gestionnaire du réseau de transport. Les différents types de réglages proposés sont basés sur des algorithmes d’optimisation multi-objectifs. Afin de valider en temps réel le bon fonctionnement des stratégies de réglages développées ainsi que leurs modes de communication, une implantation expérimentale sous simulateur temps réel RT-Lab a été effectuée. Enfin, les résultats des simulations montrent l’amélioration de l’intégration de la production décentralisée dans les réseaux électriques / In this PhD dissertation, we propose various voltage and reactive power regulation algorithms for different connection types of the wind farm to the power network. Three connection types are considered here: a wind farm connected directly to the distribution network, dispersed wind turbines connected to the distribution network and a set of wind farms connected to the transmission system.A closed loop controller (Wind Farm Controller) is proposed in case of a directly connected wind farm to the distribution network.A coordinated voltage control in the presence of on load tap changer (D-CVC) is proposed in case of dispersed wind turbines connected to the distribution network. We also propose a more decentralized version of D-CVC named D2-CVC; this version can be also implemented under multi-agent system (MAS).A multi-level control system is proposed in case of a set of wind farms connected to the transmission system. It allows the wind farms to optimally participate at reactive power balancing in transmission network. All the proposed voltage algorithms are based on a multi-objective optimization function. The experimental implementation of these regulation algorithms is run under RT-Lab real-time simulator. It allows validating their real-time operation and their communication modes before the implementation on a real site.The results of the current thesis show the improvement of distributed generation integration in the power system network