Thesis (M.Sc.)--York University, 2003. Graduate Programme in Computer Science. / Typescript. Includes bibliographical references (leaves 115-117). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL:http://gateway.proquest.com/openurl?url%5Fver=Z39.88-2004&res%5Fdat=xri:pqdiss&rft%5Fval%5Ffmt=info:ofi/fmt:kev:mtx:dissertation&rft%5Fdat=xri:pqdiss:MQ99408

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Two important problems namely a versatile, efficient communication system and allocation of processors to processes are analysed. An efficient communication system has been developed, in which a central controller, the bus-master, dynamically configures the point-to-point network formed by the links of the transputers. The links are used to form a point-to-point network. An identical kernel resides on each of the nodes. This kernel is responsible for all communications on behalf of the user processes. It makes ConnectLink and ReleaseLink requests to the central controller and when the connections are made it sends the the messages through the connected link to the destination node. If direct connection to the destination node cannot be made then the message is sent to an intermediate node, the message hops through intermediate nodes until it reaches the destination node. The communication system developed provides low latency communication facility, and the system can easily be expanded to include a large number of transputers without increasing interprocess communication overhead by great extent. Another problem, namely the Module Assignment Problem (MAP) is an important issue at the time of development of distributed systems. MAPs are computationally intractable, i.e. the computational requirement grows with power of the number of tasks to be assigned. The load of a distributed system depends on both module execution times, and intermodule communication cost (IMC). If assignment is not done with due consideration, a module assignment can cause computer saturation. Therefore a good assignment should balance the processing load among the processors and generate minimum inter-processor communication (IPC) ( communication between modules not residing on the same processor). Since meeting the deadline constraint is the most important performance measure for RTDPS, meeting the response time is the most important criteria for module assignment. Understanding this we have devised a scheme which assigns processes to processors such that both response time constraints and periodicity constraints are met. If such an assignment is not possible, assignment would fail and an error would be generated. Our assignment algorithm does not take into consideration factors such as load balancing. We believe that the most important factor for RTDPS is meeting the deadline constraints and that's what our algorithm accomplishes. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / abstract / Computer Science / Doctoral / Doctor of Philosophy

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Presented in this thesis is the design and implementation of a fast, compact, and flexible multi-tasking operating system. This system is designed for use in small computers which must deliver real-time performance in extremely constrained environments. The operating system is implemented in the "C" language to allow portability between different computers systems. A number of useful features are provided which support dynamic task management, message passing, a hierarchial file system, device drivers, and a command line interpreter. Modularized construction enables the user to prune unnecessary system features for specific applications. Presently, the system is operational on a personal computer which is also used for system development. This serves as a realistic environment for testing system response to real-time events.

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by Hon-Kai, Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 102-105). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Scheduling In Real-time Systems --- p.4 / Chapter 1.3 --- Cache Memories --- p.5 / Chapter 1.4 --- Outline Of The Dissertation --- p.8 / Chapter 2 --- Related Work --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- Predictable Cache Designs --- p.9 / Chapter 2.2.1 --- Locking Cache Lines Design --- p.9 / Chapter 2.2.2 --- Partially Dynamic And Static Cache Partition Allocation Design --- p.10 / Chapter 2.2.3 --- SMART (Strategic Memory Allocation for Real Time) Cache Design --- p.10 / Chapter 2.3 --- Prefetching --- p.11 / Chapter 2.3.1 --- Introduction --- p.11 / Chapter 2.3.2 --- Hardware Support Prefetching --- p.12 / Chapter 2.3.3 --- Software Assisted Prefetching --- p.12 / Chapter 2.3.4 --- Partial Cache Hit --- p.13 / Chapter 2.3.5 --- Cache Pollution Problems --- p.13 / Chapter 2.4 --- Cache Line Replacement Policies --- p.13 / Chapter 2.5 --- Main Memory Update Policies --- p.14 / Chapter 2.6 --- Summaries --- p.15 / Chapter 3 --- Problems And Motivations --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Problems --- p.16 / Chapter 3.2.1 --- Modern Cache Architecture Is Inappropriate For Real-time Systems --- p.16 / Chapter 3.2.2 --- Intertask Interference: The Effects Of Preemption --- p.17 / Chapter 3.2.3 --- Intratask Interference: Cache Line Collision --- p.20 / Chapter 3.3 --- Motivations --- p.21 / Chapter 3.3.1 --- Improvement Of The Cache Performance In Real-time Systems --- p.21 / Chapter 3.3.2 --- Hiding of Preemption Effects --- p.22 / Chapter 3.4 --- Conclusions --- p.25 / Chapter 4 --- Proposed Real-Time Cache Design --- p.26 / Chapter 4.1 --- Introduction --- p.26 / Chapter 4.2 --- Concepts Definition --- p.26 / Chapter 4.2.1 --- Tasks Definition --- p.26 / Chapter 4.2.2 --- Cache Performance Values --- p.27 / Chapter 4.3 --- Issues Related To Proposed Real-Time Cache Design --- p.28 / Chapter 4.3.1 --- A Task Serving Policy --- p.30 / Chapter 4.3.2 --- Number Of Private And Shared Cache Partitions --- p.31 / Chapter 4.3.3 --- Controlling The Cache Partitions: Cache Partition Table And Pro- cess Info Table --- p.32 / Chapter 4.3.4 --- Re-organization Of Task Owns Cache Partition(s) --- p.34 / Chapter 4.3.5 --- Handling The Bus Bandwidth: Memory Requests Queue ( MRQ ) --- p.35 / Chapter 4.3.6 --- How To Address The Cache Models --- p.37 / Chapter 4.3.7 --- Data Coherence Problems For Partitioned Cache Model And Non- partitioned Cache Model --- p.39 / Chapter 4.4 --- Mechanism For Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.1 --- Basic Operation Of Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.2 --- Assumptions And Rules --- p.43 / Chapter 4.4.3 --- First Round Dynamic Cache Partition Re-allocation --- p.44 / Chapter 4.4.4 --- Later Round Dynamic Cache Partition Re-allocation --- p.45 / Chapter 5 --- Simulation Environments --- p.56 / Chapter 5.1 --- Proposed Architectural Model --- p.56 / Chapter 5.2 --- Working Environment For Proposed Real-time Cache Models --- p.57 / Chapter 5.2.1 --- Cost Model --- p.57 / Chapter 5.2.2 --- System Model --- p.64 / Chapter 5.2.3 --- Fair Comparsion Between The Unified Cache And The Separate Caches --- p.64 / Chapter 5.2.4 --- Operations Within The Preemption --- p.65 / Chapter 5.3 --- Benchmark Programs --- p.65 / Chapter 5.3.1 --- The NASA7 Benchmark --- p.66 / Chapter 5.3.2 --- The SU2COR Benchmark --- p.66 / Chapter 5.3.3 --- The TOMCATV Benchmark --- p.66 / Chapter 5.3.4 --- The WAVE5 Benchmark --- p.67 / Chapter 5.3.5 --- The COMPRESS Benchmark --- p.67 / Chapter 5.3.6 --- The ESPRESSO Benchmark --- p.68 / Chapter 5.4 --- Simulations Parameters --- p.68 / Chapter 6 --- Analysis Of Simulations --- p.71 / Chapter 6.1 --- Introduction --- p.71 / Chapter 6.2 --- Trace Files Statistics --- p.71 / Chapter 6.3 --- Interpretation Of Partial Cache Hit --- p.72 / Chapter 6.4 --- The Effects Of Cache Size --- p.72 / Chapter 6.4.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.72 / Chapter 6.5 --- The Effects Of Cache Partition Size --- p.76 / Chapter 6.5.1 --- Performance Of Model 3 --- p.79 / Chapter 6.5.2 --- Performance Of Model 1 --- p.79 / Chapter 6.6 --- The Effects Of Line Size --- p.80 / Chapter 6.6.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.80 / Chapter 6.7 --- The Effects Of Set Associativity --- p.83 / Chapter 6.7.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.83 / Chapter 6.8 --- The Effects Of The Best-expected Cache Performance --- p.84 / Chapter 6.8.1 --- Performance of Model 1 --- p.87 / Chapter 6.8.2 --- Performance of Model 3 --- p.88 / Chapter 6.9 --- The Effects Of The Standard-expected Cache Performance --- p.89 / Chapter 6.9.1 --- Performance Of Model 1 --- p.89 / Chapter 6.9.2 --- Performance Of Model 3 --- p.91 / Chapter 6.10 --- The Effects Of Cycle Execution Time/Cycle Deadline Period --- p.92 / Chapter 6.10.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.92 / Chapter 7 --- Conclusions And Future Work --- p.95 / Chapter 7.1 --- Conclusions --- p.95 / Chapter 7.1.1 --- Unified Cache Model Is More Suitable In Real-time Systems --- p.99 / Chapter 7.1.2 --- Comments On Aperiodic Tasks --- p.100 / Chapter 7.2 --- Future Work --- p.100