This thesis develops a mathematical framework for analyzing the average bit error rate performance of five different selection diversity combining schemes over slow, frequency non-selective Rayleigh, Nakagami-m and Ricean fading channels. Aside from the classical selection diversity, generalized selection combining and the "maximum output" selection methods, two new selection rules based on choosing the branch providing the largest magnitude of log-likelihood ratio for binary phase shift keying signals (with and without phase compensation in the selection process) are also investigated. The proposed analytical framework is sufficiently general to study the effects of dissimilar fading parameter and unequal mean received signal strengths across the independent diversity paths. The effect of branch correlation on the performance of a dual-diversity system is also studied. The accuracies of our analytical expressions have been validated by extensive Monte-Carlo simulation runs. The proposed selection schemes based on the log-likelihood ratio are attractive in the design of low-complexity rake receivers for wideband CDMA and ultra wideband communication systems. / Master of Science

A rake receiver, which resolves multipath signals corrupted by a fading channel, is the most complex and power consuming block of a modem chip. Therefore, it is essential to design a rake receiver be efficient in hardware and power. We investigated a design of a rake receiver for the WCDMA (Wideband Code Division Multiple Access) system, which is a third generation wireless communication system. Our rake receiver design is targeted for mobile units, in which low-power consumption is highly important. We made judicious judgments throughout our design process to reduce the overall circuit complexity by trading with the performance. The reduction of the circuit complexity results in low power dissipation for our rake receiver. As the first step in the design of a rake receiver, we generated a software prototype in MATLAB. The prototype included a transmitter and a multipath Rayleigh fading channel, as well as a rake receiver with four fingers. Using the software prototype, we verified the functionality of all blocks of our rake receiver, estimated the performance in terms of bit error rate, and investigated trade-offs between hardware complexity and performance. After the verification and design trade-offs were completed, we manually developed a rake receiver at the RT (Register Transfer) level in VHDL. We proposed and incorporated several schemes in the RT level design to enhance the performance of our rake receiver. As the final step, the RT level design was synthesized to gate level circuits targeting TSMC 0.18 mm CMOS technology under the supply voltage of 1.8 V. We estimated the performance of our rake receiver in area and power dissipation. Our experimental results indicate that the total power dissipation for our rake receiver is 56 mW and the equivalent NAND2 circuit complexity is 983,482. We believe that the performance of our rake receiver is quite satisfactory. / Master of Science

Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Ha's group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Ha's group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation. The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm. / Master of Science

Thanks to a small wavelength (large bandwidth) combined with a low loss transmission window around 94 GHz and 120 GHz, the 75-120 GHz frequency band in millimeter wave (mm-wave) provides a promising opportunity for high data rate long range wireless communications and high-resolution imaging systems. Large-scale phased arrays have been exploited in such application for their beam forming and null steering capabilities, resulting in high directivity and improved SNR. But growing DC power consumption (Pdiss) in such large scale arrays has become an on-going concern along with noise, linearity and phase resolution trade-offs in current phased array architectures. To address these issues, we propose a power efficient phase shifter (PS) architecture based on quadrature hybrid coupler, which leverages the benefits of conventional active and passive PSs at mm-wave. The phase shifter has low loss, resulting in low power dissipation and the power domain phase interpolation by the quadrature hybrid gives low phase error and high linearity. We design W-band (90-100 GHz) phased array transmit and receive (T/R) modules in 130 nm SiGe BiCMOS technology based on the proposed PS and our measurements show high power efficiency with the lowest power consumption at W-band to our knowledge (18mW and 26mW power dissipations at receiver (Rx) and transmitter (Tx) front-ends respectively). Rx shows 23 to 25 dB peak gain, 6 to 9.3 dB NF and Tx can deliver upto 7 dBm output power with 18% power efficiency. Moreover, our PS can achieve 5-bit phase resolution with <2 degrees RMS phase error and provides 0 dBm saturated output power at 94 GHz. The phase shifter (PS) is also scalable beyond W-band without significant loss. We demonstrate this with a 120 GHz two channel phased array receiver (Rx), where a single channel shows 15.6 dB peak gain with Pdiss=53 mW which shows one of the highest gain efficiency (gain/Pdiss) among D-band phased arrays. We can further reduce the power consumption by leveraging the bidirectional signal processing at the phased array front-end. To achieve this, we designed a W-band bidirectional variable gain amplifier with gain variation ranging from 6 to -1 dB at 94 GHz which can be used along with bidirectional PS. The amplifier will replace the lossy SPDT switch in the conventional bidirectional approach, reducing the overall power consumption. / Ph. D. / The wireless technology is pushing towards the high operating frequencies to achieve high data rate and 75-120 GHz frequency band in millimeter wave (mm-wave) are of great current interest for the backhaul communications, radar and imaging systems. However, high frequency yields high propagation loss which has been overcome with large scale phased arrays in such applications for their high directivity, narrow beam forming capabilities and implementation with silicon technologies. The high dissipation due to large number of elements is a major concern which often requires heat sinks around the sensors leading to increase in cost, size and weight. For the large silicon array to be of practical use in commercial systems, it is paramount to maintain a high power efficiency and low power dissipation in the array element. In this research, a power efficient phased array architecture has been proposed which is implemented to design transmit/receive (T/R) modules in advanced silicon technologies. Experimental results show that the proposed architecture achieves the lowest power consumption and improved power efficiency per T/R element among state-of-the-art mm-wave phased arrays. The research also proposes an alternative way to improve power efficiency of phased arrays by reusing the amplifiers in both transmit and receive path where the amplifier replaces lossy switch as well, resulting in a low loss bidirectional system which can reduce the power consumption further. Finally, we believe that this research contribution has an significant impact in the effort of building low power large-scale phased arrays at mm-wave frequencies.

During the last decade, the wireless communications industry has grown rapidly. Driven by market demand, service providers are continuously looking for better systems. The main focus of continued research has been to increase the quality of services and system capacity. The Code Division Multiple Access (CDMA) cellular system had been proposed for use as a new standard for cellular telephone systems. A great deal of research has been conducted to develop receiver structures useful for CDMA systems. Traditional receivers such as the correlation and RAKE receivers are vulnerable to the near-far problem, i.e., the problem encountered when one received signal power is stronger than another. This problem is common in mobile environments. For single-user receivers, adaptive filtering techniques can be employed to alleviate multiple access interference and the near-far problem. In this thesis, an adaptive filter receiver is implemented on the FPGA-based configurable computing platform called GigaOps G900. By using FPGAs, designers can implement special-purpose signal processing architectures using specialized data paths, optimized sequencing, and pipelining while still providing some flexibility. This results in better overall system performance, resource utilization, and reduced power consumption. / Master of Science

RF front-ends are nonlinear systems that have nonlinear frequency response and, hence, can impair receiver performance by harmful adjacent channel interference in non-intuitive ways. Next generation wireless networks will see unprecedented diversity across receiver and radio technologies accessing the same band of spectrum in spatio-temporal proximity. Ensuring adjacent channel co-existence is of prime importance for successful deployment and operations of next generation wireless networks. Vulnerabilities of receiver front-end can have a severe detrimental effect on network performance and spectrum co-existence. This dissertation addresses the technological challenges in understanding and accounting for receiver sensitivities in the design of next generation wireless networks. The dissertation has four major contributions. In the first contribution, we seek to understand how receiver nonlinearity impacts performance. We propose a computationally efficient framework to evaluate the adjacent channel interference in a given radio/spectrum environment. We develop novel tractable representation of receiver front-end nonlinearity to specify the adjacent channel signals that contribute to the interference at the desired channel and the total adjacent channel interference power at a given desired channel. In the second contribution, we seek to understand how the impact of receiver nonlinearity performance can be quantified. We quantify receiver performance in the presence of adjacent channel interference using information theoretic metrics. We evaluate the limits on achievable rate accounting for RF front-end nonlinearity and provide a framework to compare disparate receivers by forming generalized metrics. In the third contribution, we seek to understand how the impact of receiver nonlinearity can be managed at the network level. We develop novel and comprehensive wireless network management frameworks that account for the RF nonlinearity, impairments, and diversity of heterogeneous wireless devices. We further develop computationally efficient algorithms to optimize the proposed framework and examine network level performance. We demonstrate through extensive network simulations that the proposed receiver-centric frameworks provide substantially high spectrum efficiency gains over receiver-agnostic spectrum access in dense and diverse next generation wireless networks. In the fourth contribution, we seek to understand how scalable interference networks are with receiver nonlinearity. We propose practical achievable schemes for interference avoidance and assess the scalability of the next generation wireless networks with interference due to receiver nonlinearity. Further, we develop an algorithmic scheme to evaluate the upper bound on scalability of nonlinear interference networks. This provides valuable insights on scalability and schemes for nonlinear adjacent channel interference avoidance in next generation shared spectrum networks. / Ph. D. / There has been a dramatic increase in the demand for mobile data, since the introduction of smartphones. Over the air transmission of data utilizes a natural resource called radio frequency spectrum. The efficient utilization of the radio frequency spectrum and clever wireless network management is key for satisfying this demand. Besides improving the quality of wireless services, efficient spectrum utilization will also have profound economic benefits and spur growth. It has been shown that spectrum is most efficiently used when shared among various services rather than licensed to specific users and communication systems. This implies that next generation wireless networks will comprise of diverse types of wireless devices. Thus, network design and regulation should ensure their harmonious co-existence. However, the practicality of spectrum sharing technology and regulation is still in its infancy. In particular, the effect of radio receiver performance and vulnerabilities from signals in the spectral neighborhood on spectrum regulation and management is not well understood. A detailed study and analysis of this is of paramount importance spectrum sharing and regulation in next generation wireless networks. In this dissertation we develop the fundamentals, limitations, and management strategies on the impact of receiver performance on efficient spectrum access and co-existence. In addition, this key insights to maximize network efficiency in next generation wireless systems are presented. The outcome of this dissertation will aid in developing frameworks to increase social awareness about low-quality wireless devices and their implications on capacity. In summary, this dissertation provides a the necessary foundations to understand, design, and optimize the next generation wireless networks, which will have far reaching economic and social benefits.

<p>Media extenders or digital media receivers are network devices that are used to retrieve digital media files (such as music, pictures, or video) from a media server and play or show them on a TV or home theater system. A technology that is often associated with these devices is the Universal Plug and Play (UPnP) technology. This technology enables network devices to be used without requiring the user to do network configuration on it. This thesis demonstrates how a device that is normally used for receiving digital television broadcasts can be enhanced to support media extender functionality. The thesis describes the design and implementation of the technologies that are needed to accomplish this functionality. The main topics are centered around on how UPnP awareness and media rendering (decoding) are incorporated into the device.</p>

High efficiency multi-junction (MJ) solar cells were packaged onto receiver systems. The efficiency change of concentrator cells under continuous high intensity illumination was done. Also, assessment of the receiver design on the overall performance of a Fresnel-type concentration system was investigated. We present on receiver designs including simulation results of their three-dimensional thermal operation and experimental results of tested packaged receivers to understand their efficiency in real world operation. Thermal measurements from solar simulators were obtained and used to calibrate the model in simulations. The best tested efficiency of 36.5% is obtained on a sample A receiver under 260 suns concentration by the XT-30 solar simulator and the corresponding cell operating temperature is ~30.5°C. The optimum copper thickness of a 5 cm by 5 cm simulated alumina receiver design was determined to be 6 mm and the corresponding cell temperature under 1000 suns concentration is ~36°C during operation.

High efficiency multi-junction (MJ) solar cells were packaged onto receiver systems. The efficiency change of concentrator cells under continuous high intensity illumination was done. Also, assessment of the receiver design on the overall performance of a Fresnel-type concentration system was investigated. We present on receiver designs including simulation results of their three-dimensional thermal operation and experimental results of tested packaged receivers to understand their efficiency in real world operation. Thermal measurements from solar simulators were obtained and used to calibrate the model in simulations. The best tested efficiency of 36.5% is obtained on a sample A receiver under 260 suns concentration by the XT-30 solar simulator and the corresponding cell operating temperature is ~30.5°C. The optimum copper thickness of a 5 cm by 5 cm simulated alumina receiver design was determined to be 6 mm and the corresponding cell temperature under 1000 suns concentration is ~36°C during operation.

Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences.