• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 1
  • Tagged with
  • 1
  • 1
  • 1
  • 1
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

An improved method for register file verification

Quan, Tong 2009 August 1900 (has links)
Register file logic verification historically involves comparing two human generated logic sources such as a VHDL code file and a circuit schematic for logic equivalence. This method is valid for most cases, however it does not account for instances when both logic sources are equivalent but incorrect. This report proposes a method to eliminate this problem by testing logic coherency of various sources with a golden logic source. This golden logic source will be generated by a register file simulation program which has been developed to simulate accurate regfile I/O port data. Implementation of this simulation program for logic verification will eliminate the accuracy problem stated above, in addition the logic simulation time for the new method has also been reduced by 36% compared to the former method. / text

Page generated in 0.1516 seconds