Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components’ interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.

Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components’ interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.

Submitted by Daniele Amaral (daniee_ni@hotmail.com) on 2016-09-13T20:06:59Z No. of bitstreams: 1 DissGSSS.pdf: 12761989 bytes, checksum: 9e4c2b4e76a2502af072064ed081eec1 (MD5) / Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-09-15T13:34:53Z (GMT) No. of bitstreams: 1 DissGSSS.pdf: 12761989 bytes, checksum: 9e4c2b4e76a2502af072064ed081eec1 (MD5) / Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-09-15T13:35:23Z (GMT) No. of bitstreams: 1 DissGSSS.pdf: 12761989 bytes, checksum: 9e4c2b4e76a2502af072064ed081eec1 (MD5) / Made available in DSpace on 2016-09-15T13:35:30Z (GMT). No. of bitstreams: 1 DissGSSS.pdf: 12761989 bytes, checksum: 9e4c2b4e76a2502af072064ed081eec1 (MD5) Previous issue date: 2014-11-19 / Não recebi financiamento / Loop pipelining is a technique that may offer significant performance improvements, being employed not only in conventional compilation targeting microprocessors, but also by High Level Synthesis (HLS) tools, targeting heterogeneous architectures and hardware accelerators. This work presents a specialized hardware support aiming at facilitate compilation tasks for HLS tools, along with potential advantages in execution performance and total silicon area employed. Two specialized hardware modules are presented: a queue register file and an instruction predication control module. / O desempenho na execução de programas, que é cada vez mais uma prioridade, pode ter uma melhora significativa por meio do uso de paralelismo em nível de instrução (ILP). Uma técnica que utiliza o ILP e propicia ganhos de desempenho significativos é o loop pipelining, sendo usado não apenas por compiladores para microprocessadores, mas também por ferramentas de Síntese de Alto Nível (HLS), visando arquiteturas heterogêneas e aceleradores de hardware. Neste trabalho é apresentado o projeto e implementação de estruturas de hardware especializadas, objetivando-se em solucionar o problema de sobreposição de valores que ocorre no loop pipelining, facilitar tarefas de compilaçãoo em ferramentas HLS e diminuir a repetição de código. Além disso, ganhos potenciais de desempenho e área de silício total podem ser alcançados como resultado do uso das estruturas propostas. Serão apresentados: um arquivo de registradores baseado em filas e um módulo de controle para a execução de instruções predicadas.