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The all terminal reliability of a graph G is the probability that at least a spanning tree is operational, given that vertices are always operational and edges independently operate with probability p in [0,1]. In this thesis, an investigation of all terminal reliability is undertaken. An open problem regarding the non-existence of optimal graphs is settled and analytic properties, such as roots, thresholds, inflection points, fixed points and the average value of the all terminal reliability polynomial on [0,1] are studied. A new reliability problem, the k -clique reliability for a graph G is introduced. The k-clique reliability is the probability that at least a clique of size k is operational, given that vertices operate independently with probability p in [0,1] . For k-clique reliability the existence of optimal networks, analytic properties, associated complexes and the roots are studied. Applications to problems regarding independence polynomials are developed as well.

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An integrated circuit can now contain more than one billion transistors. With increasing system integration and technology scaling, power and power-related issues have become the primary challenges of integrated circuit design. In this dissertation, techniques and algorithms, from system-level synthesis to emerging integration and device technologies, are proposed to address the power and power-induced thermal and reliability challenges of modern billion-transistor integrated circuit design. In Chapter 1, the challenges of semiconductor technology scaling are introduced. Chapter 2 reviews the related works. Chapter 3 focuses on the reliability optimization issue during system-level design. A reliable application-specic multiprocessor system-on-chip synthesis system is proposed, called TASR, which exploits redundancy and thermal-aware design planning to produce reliable and compact circuit designs. Chapter 4 introduces three-dimensional (3D) integration, a new integrated circuit fabrication and integration technology. Thermal issue is a primary concern of 3D integration. A 3D integrated circuit heat flow analytical framework is proposed in this chapter. Proactive, continuously-engaged hardware and operating system thermal management techniques are presented and evaluated which optimize system performance than state-of-the-art techniques while honoring the same temperature bound. Chapter 5 presents reconfigurable architecture design using single-electron tunneling transistor, an ultra-low-power nanometer-scale device. The proposed design has the potential to overcome the power and energy barriers for both high-performance computing and ultra-low-power embedded systems. Conclusions are drawn in Chapter 6. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-07-02 19:24:18.632