With rapid progress in microelectronics technology, high-performance Integrated Circuits (ICs) bring huge challenge to design the power supplies. Fast loop response is required to handle the high transient current of devices. Power solution size is demanded to reduce due to the size reduction of integrated circuits. The best way to meet these harsh requirements is to increase switching frequency of power supplies. Along with the benefits of increasing switching frequency, the power supplies will suffer from high switching loss and high gate charge loss as these losses are frequency dependant losses. This thesis investigates the best topology to minimize the switching loss. The Series-Parallel Resonant Converter (SPRC) with current-doubler is mainly analyzed for high frequency low voltage high current application. The advantages and disadvantages of SPRC with current-doubler are presented. A new adaptive synchronous rectifiers timing control scheme is also proposed. The proposed timing control scheme demonstrates it can minimize body diode conduction loss of synchronous rectifiers and therefore improve the efficiency of the converter. This thesis also proposes two families of new resonant gate drive circuits. The circuits recover a portion of gate drive energy that is total lost in conventional gate drive circuit. In addition to reducing gate charge loss, it also reduces the switching losses of the power switches. Detail operation principle, loss analysis and design guideline of the proposed drive circuits are provided. Simulation and experimental results are also presented. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-01-29 22:37:09.812

Improved transient performance and converter miniaturization are the major driving factors behind high frequency operation of switching power supplies. However, high speed operation is limited by topology, control, semiconductor, and packaging technologies. The inherent mitigation of switching loss in resonant converters makes them prime candidates for use when the limits of switching frequency are pushed. The goal of this thesis is to address two areas that practically limit the achievable switching frequency of resonant topologies. Traditional control methods based on single cycle response are impractical at high frequency; forcing the use of pulse density modulation (PDM) techniques. However, existing pulse density modulation strategies for resonant converters in dc/dc applications suffer from: • High semiconductor current stress. • Slow response and large filter size determined by the low modulating frequency. • Possibly operating at fractions of resonant cycles leading to switching loss; thereby limiting the modulating frequency. A series resonant converter with variable frequency PDM (VF-PDM) with integral resonant cycle control is presented to overcome the limitations of existing PDM techniques to enable efficient operation with high switching frequency and modulating frequency. The operation of the circuit is presented and analyzed, with a design procedure given to achieve fast transient performance, small filter size, and high efficiency across the load range with current stress comparable to conventional control techniques. It is shown that digital implementation of the controller can achieve favourable results with a clock frequency four times greater than the switching frequency. Driving the synchronous rectifiers is a considerable challenge in high current applications operating at high switching frequency. Resonant gate drivers with continuous inductor current experience excessive conduction loss, while discontinuous current drivers are subject to slow transitions and high peak current. Current source drivers suffer from high component count and increased conduction loss when applied to complementary switches. A dual-channel current source driver is presented as a means of driving two complementary switches. A single coupled inductor with discontinuous current facilitates low conduction loss by transferring charge between the MOSFET gates to reduce the number of semiconductors in the current path, and reducing the number of conduction intervals. The operation of the circuit is analyzed, and a design procedure based on minimization of the total synchronous rectifier loss is presented. Implementation of the digital logic to control the driver is discussed. Experimental results at megahertz operating frequencies are presented for both areas addressed to verify the theoretical results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2012-09-09 20:43:56.997