Thesis (Ph. D.)--Washington State University, August 2006. / Includes bibliographical references (p. 129-133).

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 97-98).

Thesis (Ph. D.)--Washington State University, August 2007. / Includes bibliographical references (p. 126-134).

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 53-56). Also available in electronic version.

Thesis (M. Sc.)(Computer Science)--University of Pretoria, 2006. / Includes summary. Includes bibliographical references. Available on the Internet via the World Wide Web.

Information dissemination is an important issue for mobile ad-hoc communities. This issue is very challenging due to the dynamic and fragile nature of the mobile ad-hoc networks, in which participants have limited computing resources and battery, intermittent network connections, and mobile tasks. To address the aforementioned issue, this thesis proposes an efficient semantics-based publish/subscribe strategy. In our proposed publish/subscribe system, distributed mobile participants are organized into clusters based on their location proximity. A compact semantics-based indexing scheme is provided to guide information flow. Intra- and inter- cluster routings are proposed to assist efficient propagation of event notifications. A comprehensive set of simulation experiments prove the effectiveness of the proposed scheme.

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware. / FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques. / On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture. / On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system. / Tang, Wai Chung. / Adviser: David Yu-Liang Wu. / Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3704. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 70-74). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Li Fengjun. / Thesis submitted in: July 2004. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 83-84). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.v / Table of Contents --- p.vi / List of Figures --- p.viii / List of Tables --- p.ix / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations of this work --- p.1 / Chapter 1.2 --- Network Fairness Issue --- p.3 / Chapter 1.3 --- Our Contribution --- p.4 / Chapter 1.4 --- Organization of the Thesis --- p.5 / Chapter Chapter 2 --- Background of Fairness Index --- p.7 / Chapter 2.1 --- The Model --- p.7 / Chapter 2.2 --- Definitions of Fairness Index --- p.9 / Chapter 2.3 --- General Existence and Uniqueness Properties of Perfectly Fair Solution --- p.12 / Chapter 2.4 --- Properties in Specific Network Topologies --- p.16 / Chapter 2.4.1 --- Uniform Routing Networks --- p.16 / Chapter 2.4.2 --- Single Routing Node Networks --- p.20 / Chapter Chapter 3 --- Extension of the Fairness Index --- p.22 / Chapter 3.1 --- A Single Routing Node Network Example --- p.22 / Chapter 3.2 --- The Max-Min Fairness Index --- p.27 / Chapter 3.3 --- Von Neumann Equilibrium Index --- p.29 / Chapter Chapter 4 --- Distributed Low Bit Rate Algorithm --- p.36 / Chapter 4.1 --- Distributed Controller --- p.36 / Chapter 4.2 --- Convergence of the Low Bit Rate Distributed Algorithm --- p.39 / Chapter 4.3 --- Experiment Results --- p.49 / Chapter 4.4 --- Heuristic Iterative Algorithm --- p.53 / Chapter Chapter 5 --- Fairness Index Based Routing --- p.57 / Chapter 5.1 --- Routing Protocol Basics --- p.58 / Chapter 5.1.1 --- Static Routing and Dynamic Routing --- p.58 / Chapter 5.1.2 --- Routing Metrics --- p.59 / Chapter 5.1.3 --- Distance Vector and Link State --- p.60 / Chapter 5.1.4 --- Shortest Path Routing Algorithm --- p.62 / Chapter 5.2 --- Minimum Delay Routing --- p.63 / Chapter 5.3 --- Fairness Index Based Routing --- p.66 / Chapter 5.3.1 --- Problem Formulation --- p.66 / Chapter 5.3.2 --- Cost Function --- p.69 / Chapter 5.3.3 --- Implementing Fairness Index Based Routing --- p.71 / Chapter 5.3.4 --- Experiment and Analysis --- p.73 / Bibliography --- p.82

This dissertation reports on studies of the application of lexicographic graph searches to solve problems in FPGA detailed routing. Our contributions include the derivation of iteration limits for scalar implementations of negotiation congestion for standard floating point types and the identification of pathological cases for path choice. In the study of the routability-driven detailed FPGA routing problem, we show universal detailed routability is NP-complete based on a related proof by Lee and Wong. We describe the design of a lexicographic composition operator of totally-ordered monoids as path cost metrics and show its optimality under an adapted A* search. Our new router, CornNC, based on lexicographic composition of congestion and wirelength, established a new minimum track count for the FPGA Place and Route Challenge. For the problem of long-path timing-driven FPGA detailed routing, we show that long-path budgeted detailed routability is NP-complete by reduction to universal detailed routability. We generalise the lexicographic composition to any finite length and verify its optimality under A* search. The application of the timing budget solution of Ghiasi et al. is used to solve the long-path timing budget problem for FPGA connections. Our delay-clamped spiral lexicographic composition design, SpiralRoute, ensures connection based budgets are always met, thus achieves timing closure when it successfully routes. For 113 test routing instances derived from standard benchmarks, SpiralRoute found 13 routable instances with timing closure that were unroutable by a scalar negotiated congestion router and achieved timing closure in another 27 cases when the scalar router did not, at the expense of increased runtime. We also study techniques to improve SpiralRoute runtimes, including a data structure of a trie augmented by data stacks for minimum element retrieval, and the technique of step tomonoid elimination in reducing the retrieval depth in a trie of stacks structure.

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 180-187).