While FPGA interconnect networks were originally designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create connections between pins and specific wires in the interconnect. These pin-to-wire connections are motivated by both a desire to employ routing-by-abutment, in modular, pre-laid out systems, and to make direct use of resources in the fabric itself. The goal of this work is to measure the difficulty of forming such pin-to-wire connections. We show that compared to a flat placement of the complete system, the routed wirelength and critical path delay increase by 6% and 15% respectively, and the router effort increases 3.5 times. We show that while pin-to-wire connections impose increased stress on the router, they can be used under some circumstances. We also measure the impact of increasing routing architecture flexibility on these results, and propose a low-cost enhancement to improve pin-to-wire routing.

While FPGA interconnect networks were originally designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create connections between pins and specific wires in the interconnect. These pin-to-wire connections are motivated by both a desire to employ routing-by-abutment, in modular, pre-laid out systems, and to make direct use of resources in the fabric itself. The goal of this work is to measure the difficulty of forming such pin-to-wire connections. We show that compared to a flat placement of the complete system, the routed wirelength and critical path delay increase by 6% and 15% respectively, and the router effort increases 3.5 times. We show that while pin-to-wire connections impose increased stress on the router, they can be used under some circumstances. We also measure the impact of increasing routing architecture flexibility on these results, and propose a low-cost enhancement to improve pin-to-wire routing.

As the field of Delay Tolerant Networking continues to expand and receive more attention, a new class of routing algorithms have been proposed that are specifically tailored to perform in a network where no end to end paths between devices are assumed to exist. As the number of proposed routing algorithms has grown, it has become difficult to fully understand their similarities and differences. Although published results clearly show different performance results between algorithms, it can be difficult to pinpoint which of their characteristics are most responsible for their performance differences. This thesis proposes an architectural framework to define the underlying features that Delay Tolerant Network routing algorithms are composed of. Popular routing algorithms from research are discussed and shown to be compositions of the proposed architectural features, thereby validating the architecture itself. The architectural framework is also shown to be a useful guide to developing a modular and configurable simulation platform. Algorithms from literature were implemented as a composition of features, which can easily be modified and combined later to define and implement new algorithms. Better understanding the underlying structure and similarities between different routing algorithm approaches is key to truly analyzing their performance and obtaining a deep understanding of which components of an algorithm have the most influence, both positively and negatively, on the results. Armed with this knowledge, designers of Delay Tolerant Networks can more easily determine the proper composition of routing algorithm features to best fit their needs. / text