The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach of design, analysis and simulation. The metallic SET transistors considered in this work are fabricated within the chip interconnect layers using CMOS back-end-of-line (BEOL)-compatible processing. The CMOS process integration can be divided into front-end-of-line (FEOL) and BEOL processes. The FEOL includes processes required to form isolated CMOS transistors whereas BEOL is the second portion of the IC fabrication where the devices get interconnected through the wiring using multiple layers of dielectrics and metals. Therefore, metallic SET circuits can be easily stacked above the CMOS platform presenting a low cost, low thermal budget, improving the overall yield at high-volume production of highly integrated systems. This considerably decreases the interconnect parasitics and increases the density of functions while maintaining the overall acceptable performance. Many problems such as low current drivability, delay and small voltage gain that hinder SET technology for its implementation in integrated circuits can be alleviated by intelligent circuit design. Although a complete replacement of CMOS by SETs is unlikely in the near future, an augmentation of CMOS with SETs is desirable if interfacing from and to CMOS works well. Interfacing from CMOS to SET circuitry is simple as the current and voltage levels are small and in accessible range. But interfacing CMOS from SET circuits is delicate due to SET logic's low current driving capability for CMOS and its interconnect. There is no concrete research on the interface issue wherein a SET-only circuitry drives a CMOS and its interconnects. For such hybridization to become possible, it is necessary to demonstrate the SET logic driving capability for CMOS with sufficient current drive and output voltage. The core SET logic can be designed to operate at low voltage, but at the interface the output of the SET logic must be in a voltage range that can be fed to a CMOS input for proper logic functionality. It is hence necessary to develop and adopt a systematic design methodology for such hybrid circuits at a specific technology node for room temperature operation. In this thesis we will look at a generalized design methodology that can be applied to (a) develop a fabrication model with parasitic effect of a hybrid SET-CMOS and SET-only circuits, (b) design and analyze the SET based fundamental building block in hybrid SET-CMOS or SET-only circuit and (c) simulate such a circuitry to assess its merits. More specifically, we will address the interfacing issue of such hybrid circuits in which we exploit the maximum capability of a SET logic in terms of driving capability, voltage response and power for a room temperature operation. The result of this research motivates the application of SET logic in 2 stages realizing some properties beyond those of CMOS devices. The first stage is the heterogeneous integration at chip level around a CMOS core. In such a circuitry, the SET introduces new functionalities such as reconfigurable logic, random number-based circuits, and multiband filtering circuits that can be combined with CMOS based general purpose processors or I/O signal restoration. The second stage of application is to use a new information processing technology focussed on a "new switch" exploiting a new state variable to provide functional scaling substantially beyond that attainable solely with ultimately scaled CMOS.