<p>The aim of this pro ject was to evaluate the use of SIMD array architectures in radar </p><p>signal processing. This has been done by implementing one of the most demanding parts </p><p>of the radar signal processing chain for airborne radar on the CSX600 architecture devel- </p><p>oped by Clearspeed Technologies. The CSX600 architecture is a SIMD processor with 96 </p><p>processing elements which can be arranged either as a linera array or as a ring. The QR- </p><p>decomposition, which was the part chosen for implementation, is the most performance </p><p>demanding part of the STAP stage. In order to create a relevant test case the well known </p><p>RT STAP benchmark from Mitre Corporation has been used. Two different algorithms </p><p>for performing QR-decompositions have been implemented and verified. In both cases </p><p>it has been concluded that either longer (> </p><p>≈256) or shorter (< ≈32) processor array </p><p>lengths would, in general, yield a higher utilization ratio. The FLOP count and utiliza- </p><p>tion has been measured for both algorithms, and it has been concluded that at least eight </p><p>CSX600 processors are needed to meet the real-time demand of the benchmark.</p>

The aim of this pro ject was to evaluate the use of SIMD array architectures in radar signal processing. This has been done by implementing one of the most demanding parts of the radar signal processing chain for airborne radar on the CSX600 architecture devel- oped by Clearspeed Technologies. The CSX600 architecture is a SIMD processor with 96 processing elements which can be arranged either as a linera array or as a ring. The QR- decomposition, which was the part chosen for implementation, is the most performance demanding part of the STAP stage. In order to create a relevant test case the well known RT STAP benchmark from Mitre Corporation has been used. Two different algorithms for performing QR-decompositions have been implemented and verified. In both cases it has been concluded that either longer (> ≈256) or shorter (< ≈32) processor array lengths would, in general, yield a higher utilization ratio. The FLOP count and utiliza- tion has been measured for both algorithms, and it has been concluded that at least eight CSX600 processors are needed to meet the real-time demand of the benchmark.