This dissertation describes efficient design of tamper-resistant secure processor and cryptographic memory protection model that will strength security of a computing system. The thesis proposes certain cryptographic and security features integrated into the general purpose processor and computing platform to protect confidentiality and integrity of digital content stored in a computing system's memory. System designers can take advantages of the availability of the proposed security model to build future security systems such as systems with strong anti-reverse engineering capability, digital content protection system, or trusted computing system with strong tamper-proof protection. The thesis explores architecture level optimizations and design trade-offs for supporting high performance tamper-resistant memory model and micro-processor architecture. It expands the research of the previous studies on tamper-resistant processor design on several fronts. It offers some new architecture and design optimization techniques to further reduce the overhead of memory protection over the previous approaches documented in the literature. Those techniques include prediction based memory decryption and efficient memory integrity verification approaches. It compares different encryption modes applicable to memory protection and evaluates their pros and cons. In addition, the thesis tries to solve some of the security issues that have been largely ignored in the prior art. It presents a detailed investigation of how to integrate confidentiality protection and integrity protection into the out-of-order processor architecture both efficiently and securely. Furthermore, the thesis also expands the coverage of protection from single processor to multi-processor.

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Ensuring information security and scalable performance are critical in modern processor architecture designs. High-performance, data-intensive applications demand robust microarchitectures that are both secure-by-design and efficient. This dissertation explores new information leakage threats in modern processors and proposes secure-by-design architectures for emerging systems. First, we examine vulnerabilities in existing microarchitectures, focusing on speculative execution's security implications. We reveal that branch predictor designs in modern processors are speculatively updated, leading to a novel speculative execution side channel. We propose a secure branch predictor architecture to mitigate this issue while maintaining performance benefits. Second, we address challenges with emerging non-volatile memory (NVM) technologies. We identify performance-limiting characteristics of resistive-memory-based NVMs, particularly variable write latency. We present a processor-side framework to optimize NVM write latency and design a secure architecture compatible with the NVMe protocol to protect data in high-speed NVMe storage devices. Lastly, we emphasize the importance of composability in security when analyzing modern microarchitectures. We explore side channels in secure processor architectures that provide hardware-based data confidentiality and integrity protection. Our research highlights the need to synergistically understand microarchitecture security as new mechanisms are integrated. Overall, this dissertation enhances our understanding of security and performance in modern computing systems and offers solutions to their challenges. We highlight the importance of a holistic approach to security and performance to effectively integrate new technologies into modern systems.

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